Sub-Threshold Voltage Operated High Speed Domino Logic OR and AND Gates

Abstract

This paper demonstrate a new design technique for the implementation of sub-threshold voltage range domino logic gates using MOSFETs. The paper shows the implementation of the sub-threshold voltage domino logic for OR, and AND gates. These circuits work in the sub-threshold voltage range, hence, drastically reducing power consumption. This is achieved by adding a voltage boosting block that is introduced with the value of a capacitor of 1 pF which creates a faster and power-efficient pull-down network. These proposed circuits are operated at sub-threshold voltages. These circuits are simulated with +0.3 V supply voltage to yield results with good driving capability and good noise margins. The proposed circuits are designed using gpdk 180 nm CMOS design process using an LTspice tool.