Successive approximation analog-to-digital conversion at video rates

Saul, P.H.

doi:10.1109/jssc.1981.1051564

Cited by 12 publications

(3 citation statements)

References 4 publications

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“…A generalized block diagram of a successive-approximation converter is shown in [21] or current steering architecture [22]. But in most low-power implementations of the successive-approximation algorithm, the D/A converter is based on the chargeredistribution principle which is implemented as a simple switched-capacitor network [23].…”

Section: Basic Architecturementioning

confidence: 99%

A time-based energy-efficient analog-to-digital converter

Yang

Sarpeshkar

2005

IEEE J. Solid-State Circuits

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Dual-slope converters use time to perform analog-to-digital conversion but require 2 N +1 clock cycles to achieve N bits of precision. We describe a novel algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive sub-ranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating Voltage-to-Time and Timeto-Voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an efficient mechanism for amplification and error cancellation allow for energy-efficient operation: In a 0.35 µm implementation, we were able to achieve 12 bits of DNL limited precision or 11 bits of thermal noise-limited precision at a sampling frequency of 31.25kHz with 75µW of total analog and digital power consumption. These numbers yield a thermal noise-limited energy-efficiency of 1.17pJ per quantization level making it one of the most energy-efficient converters to date in the 10 to 12 bit precision range. This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18µm process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.

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Section: Basic Architecturementioning

confidence: 99%

A time-based energy-efficient analog-to-digital converter

Yang

Sarpeshkar

2005

IEEE J. Solid-State Circuits

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“…The digital tuning signal Vcontrol_Cc was determined by the calibration algorithm. After the calibration, the tuning capacitor Cc was determined through Equation (7). Ideally, good matching means that the LSB segment presents the same contribution as the unit capacitor Cu in the MSB segment.…”

Section: Mismatch Calibrationmentioning

confidence: 99%

“…Several types of DAC architecture are available for implementation into a SAR ADC: capacitor-based DAC (C-DAC) [1][2][3][4][5][6], switched current DAC [7][8][9], and R-2R ladder DAC [10,11]. To reduce the DC power dissipation, the majority of SAR ADCs are based on charge redistribution algorithms using a sampled array of capacitors.…”

Section: Introductionmentioning

confidence: 99%

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Bontems

Dzahini

2023

Chips

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This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

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