Super-self-aligned back-gate/double-gate planar transistors with thick source/drain and thin silicon channel

Lin, Hao; Liu, H.; Kumar, Amitesh; Avci, Uygar E.; VanDelden, J.; Tiwari, Sandip

doi:10.1109/drc.2006.305108

Cited by 1 publication

(2 citation statements)

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“…We have employed relatively thick gate oxides-11 nm-in our devices. Due to such large oxide thickness, 300-nm pFETs show 82 mV/dec subthreshold slope, and nFETs show 100 mV/dec [10]. With scaling of the oxide thickness, near-ideal subthreshold swings should be achievable, as expected from these geometries [5].…”

Section: Results On Device Characterizationmentioning

confidence: 95%

“…The process allows a buried back-gated structure with additional interconnects to be realized on a silicon-oninsulator (SOI) substrate in which the buried oxide layer is formed with the LTO. The thickness of the transferred silicon layer correlates with the thickness of the LTO layer and can be used for placing the peak of cleavage implantation [10]. With additional silicon CMP step of high selectivity to oxide [ Fig.…”

Section: Device Fabricationmentioning

confidence: 99%

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Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

Lin

Liu²,

Kumar³

et al. 2007

IEEE Electron Device Lett.

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We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability.Index Terms-Adaptive power control, back-gate/double-gate field-effect transistor (FET), buried interconnect, strained-Si channel, super-self-alignment.

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Section: Results On Device Characterizationmentioning

confidence: 95%

Section: Device Fabricationmentioning

confidence: 99%