Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS

Rethy, Jelle Van; Danneels, Hans; Smedt, Valentijn De; Dehaene, Wim; Gielen, Georges

doi:10.1109/jssc.2013.2274831

Cited by 57 publications

(44 citation statements)

References 17 publications

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“…The final design shows a second-order BBPLL-based sensor interface for resistive sensors [21]. This interface exploits the feedback nature of the BBPLL-based sensor interface to improve the Power-Supply Rejection Ratio (PSRR) and the temperature insensitivity.…”

Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

“…This makes the interface highly robust. This design proposes a force-balanced Wheatstone bridge technique to improve the PSRR of the entire sensor interface [21]. Furthermore, the sensor-todigital conversion is incorporated in the circuitry needed to do the force-balancing, which makes extra building blocks unnecessary.…”

Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

“…10 can be seen as the conditioning circuit. It is a 4-stage Maneatis differential VCO with replica bias feedback to bias the delay cells [21]. The time-to-digital conversion is in this case done by the second-order BBPLL, which consists of the D-flip-flop as a single-bit quantizer, the first-order digital filter, the resistive DAC and the Loop VCO in the feedback path (Fig.…”

Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

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Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits

Rethy¹,

Smedt²,

Dehaene³

et al. 2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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The ever increasing demand for improved autonomy in wireless sensor devices, drives the search for new energy-efficient sensor interface topologies in CMOS technology. Recently, time-based conversion has gained a lot of interest due to its high potential to implement highly-digital circuitry. While voltage-based analog integrated circuits suffer from the decreased supply voltage and voltage swing in highly-scaled CMOS technologies, time-based processing takes advantage of the increased timing resolution. However, how do these time-based sensor interface circuits compare to their amplitude-based counterparts fundamentally? To answer this question, theoretical limits are derived in this chapter for both implementations, which shows that the sensor itself is actually the dominant factor in limiting the achievable energy efficiency. Time-based topologies, however, enable the implementation of highly-digital interfaces, which are scalable, areaefficient and have low-voltage potential. These observations are illustrated with several practical designs.

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Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

Section: Design 4: Bbpll-based Force-balanced Wheatstone Bridge Sdcmentioning

confidence: 99%

See 1 more Smart Citation

Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits

Rethy¹,

Smedt²,

Dehaene³

et al. 2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, to resolve bits, a clock frequency greater than times the sampling frequency is required. In an alternative implementation, the sensor voltage sets the oscillation frequency of a voltage-controlled oscillator [13]. However this method still requires the oscillation frequency to be much higher than the sampling rate.…”

Section: Temperature Sensors and Readout Circuitsmentioning

confidence: 99%

“…Biasing the current sources in the strong inversion region decreases at the price of higher overdrive voltage. Observing that the bias currents of transistors are proportional to their sizes we have and so we can simplify (13) to:…”

Section: Noise Analysismentioning

confidence: 99%

A 15 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm W}$</tex></formula> 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB

Ghanad

Green

Dehollain

2014

IEEE Trans. Circuits Syst. I

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A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each operation step the sensor resistance is compared with the value of a reference resistive DAC which is implemented on chip. Therefore no stable, temperature compensated reference voltage is needed for operation. Furthermore the chip is operational with supply voltages ranging from 1.2 to 1.8 volts. Detailed analyses of the circuit gain and noise are provided. In addition, the effect of circuit topology on the noise performance is discussed. The effect of noise on accuracy of the circuit is also negligible due to resetting the charge-integrating capacitor after each comparison. A prototype chip is fabricated in 0.18-CMOS. The circuit dissipates 15 with 5.5 kS/s conversion rate from a 1.5 V supply. The complete interface circuit has 14 pJ/c-s figure of merit and 7.6 effective number of bits.Index Terms-ADC, integrating, low power, medical implants, noise, successive approximation register (SAR), sensor readout, time domain comparator.

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