Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain

Siddique, Marif Daula; Mekhilef, Saad; Shah, Noraisyah Mohamed; Ali, Jagabar Sathik Mohamed; Seyedmahmoudian, Mehdi; Horan, Ben; Stojcevski, Alex

doi:10.1049/iet-pel.2020.0446

Cited by 21 publications

(13 citation statements)

References 14 publications

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“…The maximum voltage stress across all switches is the important parameter for the topology, and it can be represented as the total standing voltage (TSV), which is equal to the sum of maximum voltage stress across the switches [49][50]. This is an important factor for the selection of switches.…”

Section: Tsv (Total Standing Voltage) Calculationmentioning

confidence: 99%

A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components

et al. 2020

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In this paper, a novel three-phase asymmetrical multilevel inverter is presented. The proposed inverter is designed with an optimal hardware components to generate three-phase nineteen output voltage levels. The proposed inverter exhibits various advantages like a suitable output voltage waveform with improved power quality, lower total harmonic distortion (THD), and more moderate complexity, reduction in cost, reduced power losses, and improved efficiency. A comparison of the proposed topology in terms of several parameters with existing methods illustrates its merits and features. The proposed inverter tested with steady-state and dynamic load disturbances. Various experimental results are included in this paper to validate the performance of the proposed inverter during various extremities. In addition, a detailed comparison is tabulated between simulation and experimental results graphically. The proposed inverter has been stable even during load disturbance conditions. The simulation and feasibility model are verified using a prototype model.

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Section: Tsv (Total Standing Voltage) Calculationmentioning

confidence: 99%

A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components

et al. 2020

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“…In the proposed model [21], 16 switches with two capacitors are used to produce seven levels across the load. Similarly, with only 12 switches, the topology could generate seven levels of output voltage [22,23]. In comparison to [22,23], the structure only requires 11 switches to reach the required seven levels of output voltage [24].…”

Section: Introductionmentioning

confidence: 99%

“…Similarly, with only 12 switches, the topology could generate seven levels of output voltage [22,23]. In comparison to [22,23], the structure only requires 11 switches to reach the required seven levels of output voltage [24]. A 7L inverter with sixteen switches and two capacitors are discussed in this study [25].…”

Section: Introductionmentioning

confidence: 99%

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

Kumar¹,

Kaliamoorthy²,

Raj³

2023

Intelligent Automation &Amp; Soft Computing

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This paper presents a unique voltage-raising topology for a singlephase seven-level inverter with triple output voltage gain using single input source and two switched capacitors. The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers. The selective harmonic elimination (SHE) approach is used to remove the lower-order harmonics. The optimal switching angles for SHE is determined using the genetic algorithm. These switching angles are combined with a level-shifted pulse width modulation (PWM) technique for pulse generation, resulting in reduced total harmonic distortion (THD). A detailed comparison has been made against other relevant seven-level inverter topologies in terms of the number of switches, drivers, diodes, capacitors, and boosting facilities to emphasize the benefits of the proposed model. The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results. The Digital Signal Processing (DSP) TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

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“…The authors of [15] proposed another topology that offered lower switching stress and a higher number of levels, but the capacitors required extra attention by complex control. The topology in [16] had self-balancing capacitors, but the number of switches was high. In [17] though the topology offers high output voltage levels, it required an H-Bridge for polarity generation, thus necessitating higher rating switches.…”

Section: Introductionmentioning

confidence: 99%

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

et al. 2021

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Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

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Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain

Cited by 21 publications

References 14 publications

A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components

A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

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