Switching Activity Analysis Considering Spatioternporal Correlations

Mărculescu, Radu; Marculescu, Diana; Pedram, Massoud

doi:10.1109/iccad.1994.629783

Cited by 52 publications

(64 citation statements)

References 4 publications

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“…ACE 2.0 calculates the switching probability of the output signal from the LUT, but since the inside of the LUT is a black box, there is no information about internal activity. Thus, because the lag-one model [19] produces exact switching probabilities, the switching activity of a 2-input multiplexer is obtained by…”

Section: Switching Activity Inside Lutsmentioning

confidence: 99%

Three Dimensional FPGA Architecture with Fewer TSVs

Amagasaki

Masato

Zhao

et al. 2018

IEICE Trans. Inf. & Syst.

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SUMMARYThree-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several facedown stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized. key words: three dimensional IC, 3D-FPGA, power estimation, facedown/face-up stacking

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Section: Switching Activity Inside Lutsmentioning

confidence: 99%

Three Dimensional FPGA Architecture with Fewer TSVs

Amagasaki

Masato

Zhao

et al. 2018

IEICE Trans. Inf. & Syst.

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“…In general, if the input pattern and the spatial-temporal correlation between the data bits of a single line or two adjacent lines are available, a number of probabilistic techniques such as [13]- [15] can be used to estimate k 1 to k 5 . Furthermore, several encoding techniques have been proposed for minimizing coupling effect for static on chip bus structures [7]- [9].…”

Section: Switching Power Dissipationmentioning

confidence: 99%

Power optimal MTCMOS repeater insertion for global buses

Fatemi¹,

Amelifar²,

Pedram³

2007

Proceedings of the 2007 International Symposium on Low Power Electronics and Design

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This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-V th sleep transistors to reduce the leakage power consumption in the idle mode is used. We simultaneously calculate the repeater sizes, repeater distances, and the size of the sleep transistors to minimize the power dissipation. The effect of crosstalk coupling capacitance on propagation delay and (switching and short circuit) power dissipation is considered. Experimental results show that depending on the activity factor of the circuit, the proposed technique can significantly reduce the power consumption of the global bus interconnects.

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“…In CUM, the signal probability for a node should be calculated from its immediate fan-in. An approach possessed of this feature is called an incremental approach [3]. CUM is the most simple incremental approach.…”

Section: Previous Approachesmentioning

confidence: 99%

“…To estimate switching activities in combinational logic circuits, many probabilistic approaches were proposed [1,2,3,4,5]. In these approaches, the switching activity for an internal node is calculated from those for the primary inputs in terms of Boolean relations among nodes.…”

Section: Introductionmentioning

confidence: 99%

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Switching activity analysis for sequential circuits using Boolean approximation method

Uchino¹,

Minami²,

Murakata³

et al.

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of the sequential logic circuits.Spatio-temporal correlations are totally considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on the circuit size and it depends only on the user-specied unrolling number, which is usually 2 or 3.Experimental results show that our approach is 100-times faster than the logic simulation and 10-times more accurate than the previous approach which ignores all correlations.

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Switching Activity Analysis Considering Spatioternporal Correlations

Cited by 52 publications

References 4 publications

Three Dimensional FPGA Architecture with Fewer TSVs

Three Dimensional FPGA Architecture with Fewer TSVs

Power optimal MTCMOS repeater insertion for global buses

Switching activity analysis for sequential circuits using Boolean approximation method

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