Symbolic design space exploration for multi-mode reconfigurable systems

Abstract

Abstract-In today's complex embedded systems not all applications are running all the time, but depend on the operational mode. By incorporating knowledge about the temporal behavior of such multi-mode systems, it is possible to share hardware by means of partial reconfiguration, and thus, reduce costs and improve performance. In this paper, we specify the temporal behavior of the functionality by applying known models based on state machines. In addition, we introduce an architectural model that allows to express the characteristics of nowadays partially reconfigurable architectures, focusing on FPGAs. We develop a symbolic encoding of this novel system specification, which allows to perform a unified system synthesis for allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The proposed encoding enables the use of sophisticated optimization techniques, coupling a SAT solver with a Multi-objective Evolutionary Algorithm. The proposed methodology is highly applicable for building multi-mode systems on advanced reconfigurable technology. We demonstrate this by experiments on test-cases from the image processing domain applying state-of-the-art technology. The results show the superiority of the presented approach in terms of run-time and quality of the found solutions compared to existing system synthesis approaches.

A Survey and Comparative Study of Hard and Soft Real-Time Dynamic Resource Allocation Strategies for Multi-/Many-Core Systems

“…For an application, all the approaches employ DSE to generate multiple allocations (operating points), which are used at run-time based on the platform status and user requirements. There has also been efforts just to develop DSE approaches optimizing for various metrics, such as execution time [Angiolini et al 2006;Jia et al 2010;Wildermann et al 2011;Piscitelli and Pimentel 2012], execution time and energy consumption [Zamora et al 2007;Giovanni et al 2010], and resource utilization [Xue et al 2006;Stuijk et al 2010]. These efforts do not explore the ways to use the DSE results at run-time.…”

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

“…Many of them are Integer Linear Programming (ILP) formulations [Ghiasi et al 2004;Cordone et al 2009], which provide a mathematical formalization for this problem, and are suitable only for static systems. For dynamic scenarios, totally or partially runtime approaches have also been proposed [Noguera and Badía 2004;Haubelt et al 2005;Wildermann et al 2011;Resano et al 2005;Clemente et al 2011b]. On the one hand, Noguera and Badía [2004], propose a hardware microarchitecture to deal with DFGs applying a list-based scheduling heuristic; Haubelt et al [2005] present a slack-based list scheduler for time-multiplexed architectures; and Wildermann et al [2011] propose a design space exploration for reconfigurable embedded systems.…”

Operational mode exploration for reconfigurable systems with multiple applications

“…Thus, offline methods for task binding are more efficient to analyze the system behavior for a given specification by performing system-level synthesis. However, system-level synthesis approaches, such as the methodologies for multi-mode heterogeneous systems proposed in [9], [2], [10], need predefined operational modes, i.e., it has to be known beforehand which combinations of applications may run concurrently.…”

“…The directed edges E R indicate the communication links between resources. In the following, we give a brief overview of modeling partially reconfigurable architectures, details can be found in [10]. Reconfigurable systems are built by partitioning the reconfigurable chip area into static regions and partially reconfigurable regions (PR regions).…”

“…For example, if G 6 and G 7 are known to be the most robust image filter applications, A5 should be chosen, since only A5 allows to run G 6 and G 7 concurrently. Now, the system can be synthesized accordingly, e.g., by applying the synthesis flows for multi-mode systems from [9], [2], [10].…”