Synchronised switching [Ethernet switch]

Holmeide, Ø.; Skeie, Tor

doi:10.1049/cce:20060207

Cited by 2 publications

(4 citation statements)

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“…The precision of the NTP synchronization can be largely improved by executing the timestamping operation in lower layers [29]. However, to achieve the highest precision in the timestamping operation, the Ethernet network interface card (NIC) must carry out this task as soon as the packets arrive or leave the interface.…”

Section: Ntp Synchronizationmentioning

confidence: 99%

“…However, to achieve the highest precision in the timestamping operation, the Ethernet network interface card (NIC) must carry out this task as soon as the packets arrive or leave the interface. Therefore, accuracy in the client's clock can be within one microsecond [29]. This way, the precision of an NTP client/server system can be similar to that of a PTP systems, where hardware-assisted timestamping is mandatory in a standards-compliant implementation.…”

Section: Ntp Synchronizationmentioning

confidence: 99%

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High-Performance Time Server Core for FPGA System-on-Chip

et al. 2019

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This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

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Section: Ntp Synchronizationmentioning

confidence: 99%

Section: Ntp Synchronizationmentioning

confidence: 99%

High-Performance Time Server Core for FPGA System-on-Chip

et al. 2019

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“…As in PTP, the precision of the NTP synchronization can be largely improved by doing the time-stamping operation in lower layers [5,6,7]. The highest precision in the time-stamping operation is only achievable if done by the Ethernet device hardware as soon as the packets arrive or leave the interface.…”

Section: Fig 1 On-wire (S)ntp Protocol Operationmentioning

confidence: 99%

“…The highest precision in the time-stamping operation is only achievable if done by the Ethernet device hardware as soon as the packets arrive or leave the interface. Thus, precision at the time client can be better than one microsecond [7].…”

Section: Fig 1 On-wire (S)ntp Protocol Operationmentioning

confidence: 99%

Network Time Synchronization: A Full Hardware Approach

Juan

Viejo

Bellido

2013

Lecture Notes in Computer Science

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Abstract. Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost of paying in performance and hardware resources usage. Network time synchronization is a good example of a complex system using several abstraction levels since the traditional solutions are a software application running on top of several software and hardware layers. In this contribution we study the case where a standards-compliant network time synchronization solution is fully implemented in hardware on a FPGA chip doing without any software layer. This solution makes it possible to implement very compact, inexpensive and accurate synchronization systems to be used either stand-alone or as embedded cores. Some general aspects of the design experience are commented together with some figures of merit. As a conclusion, full hardware implementations of complex digital systems should be seen as a feasible design option, from which great performance advantages can be expected, provided that we can find a suitable set of tools and control the design development costs.

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Synchronised switching [Ethernet switch]

Cited by 2 publications

References 0 publications

High-Performance Time Server Core for FPGA System-on-Chip

High-Performance Time Server Core for FPGA System-on-Chip

Network Time Synchronization: A Full Hardware Approach

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