Synchronous VME64x Block Transfers with Bus-Invert Coding For Low Noise, Low Power Performance

Abstract

The VME64x standard defines a double edge source synchronous block transfer (2eSST) capable to sustain a data transfer rate up to 320 MByte/s on the VMEbus. This level of performance is achieved by double edge clocking a 64-bit bus with bursts of data strobe pulses. The switching activity of such a wide bus on a shared backplane challenges the signal integrity and the data transfer reliability. The BusInvert is a well known coding technique developed to lower the peak power dissipation in I/O busses by decreasing their switching activity. In this paper we discuss how the BusInvert coding can be applied to improve the 2eSST performance. The hardware overheads introduced by the encoding algorithm is discussed in the view of deployments in low-latency, real-time applications.