Synthesis algorithm of low sensitivity non‐separableN‐D finite impulse response filters configured of fast orthogonal 1‐D rotation structures implemented in field programmable gate arrays IC

Abstract

In the article, a low sensitivity synthesis algorithm of a non-separable N-dimensional (N-D) finite impulse response filter implemented in Field Programmable Gate Arrays (FPGA) is proposed. The synthesis and implementation algorithms determine a pipelined non-separable N-D finite impulse response filter structure consisting of fast Givens rotator structures. The filter transfer function is expressed as a function of N independent 1-D orthogonal transfer functions in each of N directions to avoid difficult, multidimensional equation computation. The rotator structure is obtained using the COR-DIC algorithm. The proposed synthesis algorithm was used to design and optimise the structure of the Laplacian of Gaussian (LoG) 3-D filter. The obtained filter was implemented in FPGA IC and its parameters, sensitivity, processing time and signal-toquantisation noise ratio, were simulated and measured. The assessed results were compared with the theoretical analysis of the filter parameters. In order to verify the advantages of the proposed filtering solution, the parameter results were compared with the results of the convolution direct implementation and the orthogonal/non-orthogonal state-space implementation of the LoG 3-D filter.