Synthesis-for-testability of controller-datapath pairs that use gated clocks

Nourani, M.; Carletta, J.; Papachristou, C.

doi:10.1109/dac.2000.855386

Cited by 1 publication

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“…This issue was recognized and examined from the early stages of CG development [38,39] with an emphasis on the observability of state machines with gated clocks. This issue was recognized and examined from the early stages of CG development [38,39] with an emphasis on the observability of state machines with gated clocks.…”

Section: Design For Testability Considerations and Approachesmentioning

confidence: 99%

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

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Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

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Section: Design For Testability Considerations and Approachesmentioning

confidence: 99%

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

Synthesis-for-testability of controller-datapath pairs that use gated clocks

Cited by 1 publication

References 18 publications

Clock gating methodologies and tools: a survey

Clock gating methodologies and tools: a survey

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