Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations

Abstract

The implementation of real-time signal processing applications calls for parallelism to avoid unpractical clock frequencies and to lower power consumption. In this paper, a method for exploring the design space of parallel elementary computing resources is proposed. The method can be used to find a suitable set of computing resources for processors applying instruction level parallelism (ILP) or pure hardware designs. The extensive size of the design space is coped with coarse level modeling and evaluation. The method presents the system as a union of multisets of computing resources. This formulation provides a general framework for efficient, multi-objective optimization in terms of relevant cost metrics, including processing latency, area, and power consumption. We demonstrate this framework by developing a multiobjective evolutionary algorithm based on it, and applying this algorithm to a rake receiver application.