Synthesis of regular computational fabrics with ambipolar CNTFET technology

Marchi, Michele De; Bobba, Shashikanth; Jamaa, M. Haykel Ben; Micheli, Giovanni De

doi:10.1109/icecs.2010.5724456

Cited by 3 publications

(8 citation statements)

References 11 publications

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“…In [20], a library of static ambipolar gates based on generalized NOR-NAND-AOIs is proposed that efficiently implements XOR-based functions. Various novel reconfigurable blocks with embedded XOR blocks have been proposed that leverage upon embedded XOR functionality [22]. Zukoski et al [21] proposed universal logic modules that leverage ambipolar transistors.…”

Section: Previous Design Approachesmentioning

confidence: 99%

“…Several novel circuit designs and architectures have been proposed that leverage upon ambipolar logic with embedded XOR functionality [20]- [22]. De Marchi et al [22] have presented the idea of regular logic fabrics and evaluated various complex gates (combination of AND-XOR-OR-INV) based on the number of subfunctions each gate can implement.…”

Section: B Layout Techniques For Xnumixed Functionmentioning

confidence: 99%

“…De Marchi et al [22] have presented the idea of regular logic fabrics and evaluated various complex gates (combination of AND-XOR-OR-INV) based on the number of subfunctions each gate can implement. A key observation is that 2-input XOR/XNOR gates form the main building block of most logic cells, especially used in data-path design and within arithmetic building blocks.…”

Section: B Layout Techniques For Xnumixed Functionmentioning

confidence: 99%

“…Fig. 14(a) shows an efficient reconfigurable logic block (F1) with ambipolar transistors, which can implement 12 different subfunctions [22]. Once the DSD is extracted from optimal transistor ordering, the final layout of the circuit is done by considering the sizing of the transistors for uniform delay caused by the transistors in the PUN and PDN.…”

Section: Relevant Examplesmentioning

confidence: 99%

“…By technology mapping onto SoT architecture, with different tiles, we investigated an optimal tile by benchmarking various circuits. We show how tiles form the basic building block for various novel design styles, which are unique to transistors with controllable polarity [21], [22].…”

Section: Sea-of-tilesmentioning

confidence: 99%

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Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Bobba

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes inherently exhibit ambipolar behavior. While technologists aim to suppress ambipolar behavior of these transistors, new design methodologies are proposed by exploiting the phenomenon of controllable polarity. In this paper, we propose regular layout fabrics, with an emphasis on silicon nanowires (SiNWs) as the candidate technology. A double-gate ambipolar SiNW field-effect transistor operates as p-type or n-type by electrically controlling the polarity of the second gate. We propose layout techniques to address gate-level routing congestion, as every transistor has two gates to route. Novel symbolic layouts, which are technology independent, are proposed for ambipolar circuits. In the second part of this paper, we present an approach for designing an efficient regular layout called sea-of-tiles (SoTs). A logic tile is essentially an array of prefabricated transistor-pairs grouped together. We design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks onto the SoT fabric to find the optimum tile. This paper shows that SoT with Tile G2 and Tile G1h2 , on an average, outperforms the one with Tile G1 by 16% and 14% in area utilization, respectively.

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Section: Previous Design Approachesmentioning

confidence: 99%

Section: B Layout Techniques For Xnumixed Functionmentioning

confidence: 99%

Section: B Layout Techniques For Xnumixed Functionmentioning

confidence: 99%

Section: Relevant Examplesmentioning

confidence: 99%

Section: Sea-of-tilesmentioning

confidence: 99%

See 3 more Smart Citations

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Bobba

Micheli

2015

IEEE Trans. VLSI Syst.

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Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Marchi

Sacchetto

Zhang

et al. 2014

IEEE Trans. Nanotechnology

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Abstract-As the current MOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n-or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I on /I off > 10 6 and subthreshold slopes approaching the thermal limit, SS ≈ 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

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Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors

Bobba

Gaillardon

Zhang

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/design co-optimization approach for designing logic tiles for double-gate silicon nanowire field effect transistors (DG-SiNWFET) technology. A compact Verilog-A model of the device is extracted from TCAD simulations. Cell libraries with different tile configurations are mapped to study the performance of DG-SiNWFET technology at various technology nodes. With an optimal tile size comprising of 6 vertically-stacked nanowires, we observe 1.6x improvement in area, 2x decrease in the leakage power and 1.8x improvement in delay when compared to Si-CMOS.I.

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Synthesis of regular computational fabrics with ambipolar CNTFET technology

Cited by 3 publications

References 11 publications

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors

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