Synthesisable glitch‐less phase rotator with conditionally cascading scheme

Abstract

This Letter presents a synthesisable phase rotator (PR) which operates without switching glitches that are reported in conventional implementations. The proposed conditionally cascading PR (CCPR) is comprised of two multiplexers (MUXes) with logic gates, and a phase interpolator (PI). This composition enables the automatic design flow through hardware description language which shortens the design time. With the MUXes operating as a cascaded PI at transition points, the proposed CCPR outputs a clock without any transient anomaly. A remarkable reduction in power and area is achieved by sharing a common PI for every pair of input clocks and merging low pass filters into the MUXes. Simulated in a 40-nm technology, the proposed CCPR consumes 1.9 mW at a 1.1 V supply with 5.4 GHz operation.