Synthesizing Embedded Speed-optimized Architectures

Abstract

A new optimal architectural synthesizer is presented for embedded chips that minimizes chip area and the average execution time in the presence of complex and asynchronous interface constraints. For the first time a model is presented for simultaneous scheduling, allocation, and selection of functional units, including chained operations to further optimize speed. This research is important for industry since we can synthesize optimal architectures with support for complex interfaces to external system components. Secondly the synthesizer selects amongst a wide range of functional units. The synthesis problem is transformed into a tight integer programming (IP) model based on polyhedral theory. A branch and bound algorithm produces globally optimal architectures in practical execution times. This research breaks new ground by 1. simultaneously scheduling and allocating with complex and asynchronous interface constraints, to minimize both the average execution time and the area, 2. automatically selecting types of functional units, including chained operations, and 3. synthesizing globally optimal architectures of embedded chips in practical execution times. A new model for synthesizing embedded VLSI chips, OAS (for optimal architectural synthesis), is introduced. The basis of this 8.7.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-0246-W92 $3.00 1992 IEEE