System-Bus Fault Injection Framework in SystemC Design Platform

Chang, Kun-Chun; Wang, Yi-Chinag; Hsu, Chung-Hsien; Leu, Kuen-Long; Chen, Yung-Yuan

doi:10.1109/ssiri.2008.11

Cited by 14 publications

(7 citation statements)

References 2 publications

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“…• Chang@2007 [30] presents the Saboteurs based FI technique for SystemC and demonstrates the usability for different levels of Transaction Level Models (TLM).…”

Section: System-level Techniquesmentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

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This thesis is the result of my work as research assistant at the Institute for Communication Technologies and Embedded Systems (ICE) at the RWTH Aachen University. During this time I have been accompanied and supported by many people. It is my great pleasure to take this opportunity to thank them. My most sincere thanks go to my advisors, Prof. Anupam Chattopadhyay and Prof. Tobias Noll. Anupam has been extremely helpful and tremendously inspiring throughout my PhD study. Prof. Noll has been impressively knowledgeable while patient with my ideas and mistakes. Their thoughtful advices have greatly contributed to this work and influenced me for my future career. Special thanks go to my defense committee members, Prof. Andrei Vescan and Prof. Renato Negra for spending their time, offering oral exam, giving me feedback, and attending my defense session. Several colleagues in ICE and EECS have assisted and encouraged me during the past five years for my work and personal life. Among them I would like to show my deep appreciation to Ayesha Khalid, Zoltán Rákossy and Michael Meixner. Furthermore, I would like to thank my students

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“…• Chang@2007 [30] presents the Saboteurs based FI technique for SystemC and demonstrates the usability for different levels of Transaction Level Models (TLM).…”

Section: System-level Techniquesmentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

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“…Thus, the work of [17] introduces fault injection methods for register transfer level (RTL) system descriptions into SystemC. Related to TLM, the work [18] presents an example of system-level fault injection in untimed functional TLM models based on FIFO channels. Related to fault tolerant TLM2 designs, the work described in [19] proposes a hardening method for inter component communication protocols.…”

Section: Papermentioning

confidence: 99%

Runtime Instrumentation of SystemC/TLM2 Interfaces for Fault Tolerance Requirements Verification in Software Cosimulation

Silva

Parra

Polo

et al. 2014

Modelling and Simulation in Engineering

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This paper presents the design of a SystemC transaction level modelling wrapping library that can be used for the assertion of system properties, protocol compliance, or fault injection. The library uses C++ virtual table hooks as a dynamic binary instrumentation technique to inline wrappers in the TLM2 transaction path. This technique can be applied after the elaboration phase and needs neither source code modifications nor recompilation of the top level SystemC modules. The proposed technique has been successfully applied to the robustness verification of the on-board boot software of the Instrument Control Unit of the Solar Orbiter’s Energetic Particle Detector.

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“…The core of the verification platform is the fault injection tool [Chang & Chen, 2007;Chen et al, 2008] under the environment of CoWare Platform Architect [CoWare, 2006], and the vulnerability analysis and risk assessment tool. The tool is able to deal with the fault injection at the following levels of abstraction [Chang & Chen, 2007;Chen et al, 2008]: bus-cycle accurate level, untimed functional TLM with primitive channel sc_fifo, and timed functional TLM with hierarchical channel. An interesting feature of our fault injection tool is to offer not only the time-triggered but also the event-triggered methodologies to decide when to inject a fault.…”

Section: System Safety Verification Platformmentioning

confidence: 99%

Vulnerability Analysis and Risk Assessment for SoCs Used in Safety-Critical Embedded Systems

Chen¹,

Juang²

2012

Embedded Systems - Theory and Design Methodology

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System-Bus Fault Injection Framework in SystemC Design Platform

Cited by 14 publications

References 2 publications

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Runtime Instrumentation of SystemC/TLM2 Interfaces for Fault Tolerance Requirements Verification in Software Cosimulation

Vulnerability Analysis and Risk Assessment for SoCs Used in Safety-Critical Embedded Systems

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