System evaluation of the Intel optane byte-addressable NVM

Peng, Ivy Bo; Gokhale, Maya; Green, Eric W.

doi:10.1145/3357526.3357568

Cited by 92 publications

(35 citation statements)

References 23 publications

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“…The control thread monitors hardware counters in PM at interval to track the write bandwidth to PM DIMMs ( ). System evaluation shows that when the concurrency level increases, the bandwidth to PM first increases to a peak and then starts decreasing [25,43,56].…”

Section: Decoupled Concurrency Control Of Clfmentioning

confidence: 99%

Ribbon

Ren

Liu

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Cache line flushing (CLF) is a fundamental building block for programming persistent memory (PM). CLF is prevalent in PM-aware workloads to ensure crash consistency. It also imposes high overhead. Extensive works have explored persistency semantics and CLF policies, but few have looked into the CLF mechanism. This work aims to improve the performance of CLF mechanism based on the performance characterization of well-established workloads on real PM hardware. We reveal that the performance of CLF is highly sensitive to the concurrency of CLF and cache line status. We introduce Ribbon, a runtime system that improves the performance of CLF mechanism through concurrency control and proactive CLF. Ribbon detects CLF bottleneck in oversupplied and insufficient concurrency, and adapts accordingly. Ribbon also proactively transforms dirty or non-resident cache lines into clean resident status to reduce the latency of CLF. Furthermore, we investigate the cause for low dirtiness in flushed cache lines in in-memory database workloads. We provide cache line coalescing as an applicationspecific solution that achieves up to 33.3% (13.8% on average) improvement. Our evaluation of a variety of workloads in four configurations on PM shows that Ribbon achieves up to 49.8% improvement (14.8% on average) of the overall application performance. CCS CONCEPTS • Hardware → Emerging technologies; • Computer systems organization → Multicore architectures; • Software and its engineering → Concurrency control.

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Section: Decoupled Concurrency Control Of Clfmentioning

confidence: 99%

Ribbon

Ren

Liu

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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“…Emerging non-volatile memory (NVM) technologies offer promising features such as byte-addressability, large storage capacity, data persistence, etc (Burr et al 2010;Zhang et al 2018Zhang et al , 2017aApalkov et al 2013). In particular, Intel release its Optane DC Persistent Memory in the middle of 2018, which could be directly attached to the memory bus and enable software to manage durable data with conventional load/store instructions (Izraelevitz et al 2019;Peng et al 2019). Durable memory transactions are popular programming models for implementing effective byte-granularity persistent data management and reasoning about the correctness of persistent memory programming (Volos et al 2011).…”

Section: Incorporating With Non-volatile Memorymentioning

confidence: 99%

A survey on optimizations towards best-effort hardware transactional memory

Lü

Wang

et al. 2020

CCF Trans. HPC

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Transactional memory has been attracting increasing attention in recent years, and it provides optimistic concurrency control schemes for shared-memory parallel programs. The rapid development and wide adoption of transactional memory make this programming paradigm promising for achieving breakthroughs in massively parallel computing. There has been a large number of discussions towards transactional memory systems, which aimed at providing relatively simple and intuitive synchronization construction for shared-memory parallel programs without sacrificing performance. Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as cache overflows, context switches, hardware as well as software exceptions, etc., nowadays HTM systems come in a best-effort way, which necessitates the adoption of a software fallback path to ensure forward progress. In this paper, we survey state-of-the-art software-side optimizations for best-effort hardware transaction system, as well as several novel performance tuning techniques. Research efforts about joint usage of HTM and non-volatile memory (NVM) are also discussed.

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“…They measured the bandwidth performance and energy characteristics of HPC applications runs on Optane DC compared to pure DRAM and DRAM as cache for Optane DC. Peng et al [16] evaluated Optane DC PMMs in all the configurations available and also measured the performance of separating read and write allocation on a DRAM/NVM memory system. All the above works focus on evaluating the basic performance characteristics of Optane DC under various execution contexts and workloads.…”

Section: Related Workmentioning

confidence: 99%

Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory

Patil

Mueller

Ionkov

et al. 2020

2020 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

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The introduction of NVDIMM memory devices has encouraged the use of DRAM/NVM based hybrid memory systems to increase the memory-per-core ratio in compute nodes and obtain possible energy and cost benefits. However, Non-Volatile Memory (NVM) is slower than DRAM in terms of read/write latency. This difference in performance will adversely affect memory-bound applications. Traditionally, data prefetching at the hardware level has been used to increase the number of cache hits to mitigate performance degradation. However, software (SW) prefetching has not been used effectively to reduce the effects of high memory access latencies. Also, the current cache hierarchy and hardware (HW) prefetching are not optimized for a hybrid memory system. We hypothesize that HW and SW prefetching can complement each other in placing data in caches and the Data Translation Look-aside Buffer (DTLB) prior to their references, and by doing so adaptively, highly varying access latencies in a DRAM/NVM hybrid memory system are taken into account. This work contributes an adaptive SW prefetch method based on the characterization of read/write/unroll prefetch distances for NVM and DRAM. Prefetch performance is characterized via custom benchmarks based on STREAM2 specifications in a multicore MPI runtime environment and compared to the performance of the standard SW prefetch pass in GCC. Furthermore, the effects of HW prefetching on kernels executing on hybrid memory system are evaluated. Experimental results indicate that SW prefetching targeted to populate the DTLB results in up to 26% performance improvement when symbiotically used in conjunction with HW prefetching, as opposed to only HW prefetching. Based on our findings, changes to GCC's prefetchloop-arrays compiler pass are proposed to take advantage of DTLB prefetching in a hybrid memory system for kernels that are frequently used in HPC applications.

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System evaluation of the Intel optane byte-addressable NVM

Cited by 92 publications

References 23 publications

Ribbon

Ribbon

A survey on optimizations towards best-effort hardware transactional memory

Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory

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