System level modeling methodology of NoC design from UML-MARTE to VHDL

Abstract

The evolution of the semiconductor technology caters for the increase in the System-on-Chip (SoC) complexity. In particular, this complexity appears in the communication infrastructures like the Network-on-Chips (NoCs). However many complex SoCs are becoming increasingly hard to manage. In fact, the design space, which represents all the concepts that need to be explored during the SoC design, is becoming dramatically large and difficult to explore. In addition, the manipulation of SoCs at low levels, like the Register Transfer Level (RTL), is based on manual approaches. This has resulted in the increase of both time-to-market and the development costs. Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) allows the modeling of repetitive structures such as the NoC topologies which are based on specific concepts. This paper presents a new methodology for modeling concepts of NoC-based architectures, especially the modeling of topology of the interconnections with the help of the repetitive structure modeling (RSM) package of MARTE profile. This work deals with the ways of improving the effectiveness of the MARTE standard by clarifying and extending some notations in order to model complex NoC topologies. Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies.

Toward the tools selection in model based system engineering for embedded systems—A systematic literature review

“…For example, all selected researches have been thoroughly studied and analyzed in order to assign them to corresponding category. Similarly, each selected research is intensively studied and Di et al, 2013, Berrani et al, 2013, Stancescu et al, 2010, Ouchani et al, 2013, Bouquet et al, 2012, DeTommasi et al, 2013, Andrade et al, 2009, Bazydlo et al, 2014, Doligalski and Adamski, 2013, Mueller et al, 2010, Durand and Bonato, 2012, Moreira et al, 2010, Vidal et al, 2009, Linehan and Clarke, 2012, Herrera et al, 2014, Lecomte et al, 2011, Rafiq Quadri et al, 2012, Chen et al, 2013, Vanderperren et al, 2008, Elhaji et al, 2012, Riccobene and Scandurra, 2012Zohaib Iqbal et al, 2013, Chouali and Hammad, 2011, Doering, 2014, Ouchani et al, 2014, Telinski Wiedermann anger et al, 2013, Knorreck and Apvrille, 2011, Ge et al, 2012, Baresi et al, 2013, Huang et al, 2012, Nguyen et al, 2014, Bousse et al, 2012 Modeling 5 Gomez et al, 2012, Penil et al, 2010, Espinoza et al, 2009, Rota Sena Marques et al, 2014, Behjati et al, 2011 Property specification 2 Yin et al, 2013…”

“…The model transformation activity has been Berrani et al, 2013, Bouquet et al, 2012, Doligalski and Adamski, 2013, Mueller et al, 2010, Greenyer and Kindler, 2010, Ko et al, 2013, Gronmo et al, 2009, Feher and Lengyel, 2012, de Lara and Guerra, 2014, Kolahdouz-Rahimi et al, 2014, Rutle et al, 2012, Huang et al, 2012 Model to Text (M2T) 9 DeTommasi et al, 2013, Moreira et al, 2010, Linehan and Clarke, 2012, Herrera et al, 2014, Zohaib Iqbal et al, 2013, Rose et al, 2012, Ledo et al, 2012, Ouchani et al, 2014 M2M and M2T 12 Giuseppe Di et al, 2013, Vidal et al, 2009, Lecomte et al, 2011, Rafiq Quadri et al, 2012, Elhaji et al, 2012, Riccobene and Scandurra, 2012, Doering, 2014, Andrea Bollati et al, 2013, Baresi et al, 2013, Bousse et al, 2012 performed in overall 35 researches. We classified these researches into three transformation types i.e.…”

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

“…Thus, this increasing number of transistor densities allows the integration of countless cores on a single chip. Therefore, it requires a powerful on-chip interconnection scheme to satisfy the communication between the large numbers of cores on chip [1]. As this communication plays a major role in determining the system performance, traditional on-chip interconnection schemes are no longer suitable for multi-Processor System on Chip (MPSoC) due to their lack of parallelism integration, scalability and resource management [2].…”

On Generating VHDL Descriptions from Aspect-Oriented UML/MARTE Models

“…[6], that are able to generate VHDL descriptions from UML models. In [7] and [8], an UML model (specially its class diagram) is used as source of information to generate a VHDL description containing only the system structure, i.e. its components and their connections.…”

“…RELATED WORKS Generating VHDL descriptions from high-level models has been proposed in various works [17], [18], [10], [8], [19]. For instance, COLA (COmponent LAnguage) tool allows system high-level specification and also the generation of a VHDL description from such a specification [18].…”