Systolic architectures for vector quantization

VLSI architectures for vector quantization

“…In their systems, a number of such devices are cascaded in order to perform the inner product computations. In this section, we compare the circuits described in this paper with those of Davidson et al [13] and highlight the attractions of the bit serial approach.…”

“…Whilst attention here has been focused on squared error distortion, it is worth noting that Davidson et al [13] have shown that almost all important distortion measures (e.g. weighted squared error, Itakura-Saito distortion measure, etc.)…”

“…Recently, Davidson et al [13] described a number of systolic architectures for VQ codebook search. These …”

“…Sections 5 and 6 then describes circuit configurations for tree search and two dimensional image processing applications. In section 7, a comparison is made between this work and important previous work in which a bit parallel data organisation is used [13]. Finally, the main conclusions of this work are presented in section 8.…”

“…For example the authors have shown how bit serial, word parallel systolic Inner Product Array (IPA) circuits can be used in the construction of VQ full search and tree search systems [11] [12]. More recently, Davidson et al [13] have described a family of systolic architectures for VQ applications. These are based on the use of a bit parallel systolic multiplier block which is based on the work of McCanny and McWhirter [15].…”