Test Chip design for study of CDM related failures in SoC designs

Olson, Nicholas; Shukla, Vrashank; Rosenbaum, Elyse

doi:10.1109/irps.2011.5784566

Cited by 7 publications

(1 citation statement)

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“…Long metal routing between receiver and driver was found to be responsible for the failed nets. It is called the long wire net effect [19,25]. The importance of low power supply wiring resistance for good ESD protection was illustrated in a 130 nm ASIC (application-specific IC) design system when premature I/O failures were found during CDM testing.…”

Section: Introductionmentioning

confidence: 99%

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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Section: Introductionmentioning

confidence: 99%

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

Huang

Ker

2021

IEEE J. Electron Devices Soc.

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The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the chargeddevice model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18-μm CMOS technology.

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