The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design

Galup-Montoro, Carlos; Schneider, M.C.; Cunha, Ana Isabela Araújo; Sousa, Francinalva Cordeiro de; Klimach, Hamilton; Siebel, O. F.

doi:10.1109/cicc.2007.4405785

Cited by 36 publications

(16 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Without any lack of generality, our analysis in this section will be based on the n-type MOSFET model; however, the formulation is applicable to p-type MOSFETs as well. It should also be noted that, as long as the source and the drain terminals are symmetric to each other, the expression in (1) holds irrespective of the choice of transistor models such as EKV (Enz, Krummenacher, and Vittoz) [13], ACM (Advanced Compact MOSFET) [14], etc. or operating regimes i.e.…”

Section: Shape-based Analog Computationmentioning

confidence: 99%

Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning

Kumar¹,

Nandi²,

Chakrabartty³

et al. 2022

Preprint

View full text Add to dashboard Cite

While analog computing is attractive for implementing machine learning (ML) processors, the paradigm requires chip-in-the-loop training for every processor to alleviate artifacts due to device mismatch and device non-linearity. Speeding up chip-in-the-loop training requires re-biasing the circuits in a manner that the analog functions remain invariant across training and inference. In this paper, we present an analog computational paradigm and circuits using "shape" functions that remain invariant to transistor biasing (weak, moderate, and strong inversion) and ambient temperature variation. We show that a core Shape-based Analog Compute (S-AC) circuit could be re-biased and reused to implement: (a) non-linear functions; (b) inner-product building blocks; and (c) a mixedsignal logarithmic memory, all of which are integral towards designing an ML inference processor. Measured results using a prototype fabricated in a 180nm standard CMOS process demonstrate bias invariance and hence the resulting analog designs can be scaled for power and speed like digital logic circuits. We also demonstrate a regression task using these CMOS building blocks.

show abstract

Section: Shape-based Analog Computationmentioning

confidence: 99%

Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning

Kumar¹,

Nandi²,

Chakrabartty³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…The ACM model, a current-mode MOSFET model that applies the concept of inversion level [3][4], provides continuous analytical functions for the transistor current from weak to strong inversion. According to the ACM model, the drain current can be split into the forward (I F ) and reverse (I R ) currents: (1) where:…”

Section: The Acm Modelmentioning

confidence: 99%

A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application

Olmos¹,

Ferreira²,

Cortes³

et al. 2020

JICS

View full text Add to dashboard Cite

This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

show abstract

“…Unfortunately, no simple analytical equation exists for the drain current of a MOSFET in moderate inversion. The EKV model [13], the BSIM model [14], the ACM model [15], and the PSP model [16] on which most simulation tools rely are too complicated for hand analysis.…”

Section: Theoretical Backgroundmentioning

confidence: 99%

Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology

et al. 2019

View full text Add to dashboard Cite

This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the g m /I D methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 µm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply. This paper aims to extend the Jespers and Murmann g m /I D -based approach [5,6] to optimize the design of a double-balanced mixer based on the Gilbert cell. A new set of lookup tables were computed to take into account the performance of the mixer in the three MOSFET inversion regions. With these new set of lookup tables, the designer is able to maximize the overall performance of the basic cell without introducing complex circuit solutions. The reported mixer was used in the design of the positioning system reported in [6][7][8][9].

show abstract

The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design

Cited by 36 publications

References 14 publications

Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning

Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning

A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application

Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology

Contact Info

Product

Resources

About