The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC

Pellegrini, Andrea; Tummala, Ashok Kumar; Jalal, Jamshed; Werkheiser, Mark; Kona, Anitha; Stephens, Nigel; Bruce, Magnus; Ishíi, Yasuo; Pusdesris, Joseph; Raja, A. Arun; Abernathy, Chris; Koppanalil, Jinson; Ringe, Tushar

doi:10.1109/mm.2020.2972222

Cited by 50 publications

(25 citation statements)

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“…If there is a MBTB miss, then the branch instruction goes to the subsequent stages of the processor pipeline to get the branch target. Instruction fetch: Instructions from the FTQ send requests to L1I ( 5 ). Since, L1I is virtually indexed, physically tagged (VIPT), ITLB is accessed to get the physical address and then L1I is accessed.…”

Section: A Designmentioning

confidence: 99%

“…Recent industry trend shows that modern processors employ a decoupled front-end [5]- [8] with a multi-level BTB design. A decoupled front-end decouples the branch prediction unit from the instruction fetch and allows the branch predictor to generate the address of future instructions.…”

Section: Introductionmentioning

confidence: 99%

“…A decoupled front-end decouples the branch prediction unit from the instruction fetch and allows the branch predictor to generate the address of future instructions. Modern processors like Arm Neoverse N1 [5], AMD Zen2 [6], Samsung Exynos M3 [7] and IBM z15 [8] have high BTB capacities of 6K, 7K, 16K and 144K entries, respectively. With technology scaling slowing down [9], the number of transistors available because of reduction in transistor size is slowing down.…”

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequent. Recent industry trend shows usage of large BTBs (100s of KB per core) that provide performance closer to the ideal BTB along with a decoupled front-end that provides efficient fetch-directed L1I instruction prefetching. On the other hand, techniques proposed by academia, like BTB prefetching and using retire order stream for learning, fail to provide significant performance with modern-day processor cores that are deeper and wider.We solve the problem fundamentally by increasing the storage density of the last-level BTB. We observe that not all branch instructions require a full branch target address. Instead, we can store the branch target as a branch offset, relative to the branch instruction. Using branch offset enables the BTB to store multiple branches per entry. We reduce the BTB storage in half, but we observe that it increases skewness in the BTB. We propose a skewed indexed and compressed last-level BTB design called MicroBTB (MBTB) that stores multiple branches per BTB entry. We evaluate MBTB on 100 industry-provided server workloads. A 4K-entry MBTB provides 17.61% performance improvement compared to an 8K-entry baseline BTB design with a storage savings of 47.5KB per core.

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Section: A Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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“…[127]- [129] Deep Learning Boost [32] CPU Pinning [130], [131] Cache Coherency Cache Hierarchy [132] DDIO [133] CPU Clock [134] Base Frequency [135] Turbo Frequency [136] Over [143] ARM Arch. in HPC RISC Design [116] Hyper-Scale Comp., Neoverse N1 ® [144], [145] ?…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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“…Buffered NoCs with virtual channel routers have been used more commonly in academic work and most recent industry standards [12,13]. Shared buffering resources, such as input and output channels, require arbitrating among different requesters.…”

Section: Introductionmentioning

confidence: 99%

Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration

Mandal¹,

Tong²,

Ayoub³

et al. 2021

Preprint

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Fast and accurate performance analysis techniques are essential in early design space exploration and pre-silicon evaluations, including software eco-system development. In particular, on-chip communication continues to play an increasingly important role as the many-core processors scale up. This paper presents the first performance analysis technique that targets networks-on-chip (NoCs) that employ weighted roundrobin (WRR) arbitration. Besides fairness, WRR arbitration provides flexibility in allocating bandwidth proportionally to the importance of the traffic classes, unlike basic round-robin and priority-based arbitration. The proposed approach first estimates the effective service time of the packets in the queue due to WRR arbitration. Then, it uses the effective service time to compute the average waiting time of the packets. Next, we incorporate a decomposition technique to extend the analytical model to handle NoC of any size. The proposed approach achieves less than 5% error while executing real applications and 10% error under challenging synthetic traffic with different burstiness levels.

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The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC

Cited by 50 publications

References 1 publication

Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration

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