The cache performance and optimizations of blocked algorithms

Lam, Monica D.; Rothberg, Edward; Wolf, Michael E.

doi:10.1145/106975.106981

Cited by 134 publications

(209 citation statements)

References 6 publications

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“…Conflict misses [20] may occur when too many data items map to the same set of cache locations, causing cache lines to be flushed from cache before they may be used, despite sufficient capacity in the overall cache. As a result, in addition to eliminating capacity misses [11], [23] and maximizing cache utilization, the tile should be selected in such a way that there are no (or few) self conflict misses, while cross conflict misses are minimized [3], [4], [5], [10], [17].…”

Section: Related Workmentioning

confidence: 99%

“…To model self conflict misses due to low associativity cache, [24] and [12] use the effective cache size q × C (q < 1), instead of the actual cache size C, while [3], [4], [10] and [19] explicitly find the non-conflicting tile sizes. Taking into account cache line size as well, column dimensions (without loss of generality, assume a column major data array layout) should be a multiple of the cache line size [4].…”

Section: Related Workmentioning

confidence: 99%

“…Taking into account cache line size as well, column dimensions (without loss of generality, assume a column major data array layout) should be a multiple of the cache line size [4]. If fixed blocks are chosen, Lam et al in [10] have found that the best square tile is not larger than aC a+1 , where a = associativity. In practice, the optimal choice may occupy only a small fraction of the cache, typically less than 10%.…”

Section: Related Workmentioning

confidence: 99%

“…What's more, the fraction of the cache used for optimal block size decreases as the cache size increases. The desired tile shape has been explicitly specified in algorithms such as [5], [3], [4], [23], [24], [10]. Both [23] and [10] search for square tiles.…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Athanasaki

Kourtis

Anastopoulos

et al. 2005

Advances in Informatics

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Abstract. Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program transformations, have been shown to be an effective approach to improving locality and cache exploitation, especially for dense matrix scientific computations. Beyond loop nest optimizations, data transformation techniques, and in particular blocked data layouts, have been used to boost the cache performance. The stability of performance improvements achieved are heavily dependent on the appropriate selection of tile sizes.In this paper, we investigate the memory performance of blocked data layouts, and provide a theoretical analysis for the multiple levels of memory hierarchy, when they are organized in a set associative fashion. According to this analysis, the optimal tile size that maximizes L1 cache utilization, should completely fit in the L1 cache, even for loop bodies that access more than just one array. Increased self-or/and cross-interference misses can be tolerated through prefetching. Such larger tiles also reduce mispredicted branches and, as a result, the lost CPU cycles that arise. Results are validated through actual benchmarks on an SMT platform.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Athanasaki

Kourtis

Anastopoulos

et al. 2005

Advances in Informatics

View full text Add to dashboard Cite

show abstract

“…Wolf et al [34] consider the integrated treatment of fusion and tiling only from the point of view of enhancing locality and do not consider the impact of the amount of required memory; the memory requirement is a key issue for the problems considered in this paper. Loop tiling for enhancing data locality has been studied extensively [27,33,30], and analytic models of the impact of tiling on locality have been developed [7,20,25]. Recently, a data-centric version of tiling called data shackling has been developed [12,13] (together with more recent work by Ahmed et al [1]) which allows a cleaner treatment of locality enhancement in imperfectly nested loops.…”

Section: Related Workmentioning

confidence: 99%

Towards Automatic Synthesis of High-Performance Codes for Electronic Structure Calculations: Data Locality Optimization

Cociorva

Wilkins

Baumgartner

et al. 2001

High Performance Computing — HiPC 2001

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Abstract. The goal of our project is the development of a program synthesis system to facilitate the development of high-performance parallel programs for a class of computations encountered in computational chemistry and computational physics. These computations are expressible as a set of tensor contractions and arise in electronic structure calculations. This paper provides an overview of a planned synthesis system that will take as input a high-level specification of the computation and generate high-performance parallel code for a number of target architectures. We focus on an approach to performing data locality optimization in this context. Preliminary experimental results on an SGI Origin 2000 are encouraging and demonstrate that the approach is effective.

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Case Studies on Cache Performance and Optimization of Programs with Unit Strides

Huang

1997

Softw: Pract. Exper.

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SUMMARYCache performance in modern computers is important for program efficiency. A cache is thrashing if a significant amount of time is spent moving data between the memory and the cache. This paper presents two cache thrashing examples, one in scientific computing and one in image processing, both of which involve several one-dimensional arrays that are accessed sequentially, i.e., with unit strides. Accessing arrays in unit strides was considered very efficient on cachebased computer systems. However, the existence of cache thrashing is demonstrated by significant increases in computing speed in the equivalent programs tuned for cache locality. This shows that accessing several arrays sequentially may cause cache thrashing. Thus, to improve cache performance, it is important that the compiler or the programmer takes all arrays inside a loop into consideration.

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The cache performance and optimizations of blocked algorithms

Cited by 134 publications

References 6 publications

Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Towards Automatic Synthesis of High-Performance Codes for Electronic Structure Calculations: Data Locality Optimization

Case Studies on Cache Performance and Optimization of Programs with Unit Strides

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