The case for a single-chip multiprocessor

Olukotun, Kunle; Nayfeh, Basem A.; Hammond, Lance; Wilson, Ken; Chang, Ken

doi:10.1145/248209.237140

Cited by 131 publications

(125 citation statements)

References 17 publications

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“…Facing issues due to high power requirements, high memory latencies and high "costs" of extracting Instruction Level Parallelism (ILP), CPU designers needed a new approach. Around 2002 they moved towards using the high transistor count to build multiple, more energy-efficient, cores on a single die [79,144]. Evolving through several generations, CMPs have become the many-cores, multithreaded, shared-cache CMPs of today [143,162].…”

Section: From Single-core To Multi-coresmentioning

confidence: 99%

“…All of them were foreseen [88, 177,181] and various architectural solutions were put forward, many of which described a CMP design. As early as 1996 Olukotun et al made their case for the development of single-chip multiprocessors [144]. Several research teams proposed architectural designs for CMPs like the Hydra [90], the Pirahna [33] or the MAJC [168] years before the industry made the switch.…”

Section: Evolution Of Cmpsmentioning

confidence: 99%

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Tuning the victim selection policy of Intel TBB

Iordan

Jahre

Natvig

2015

Journal of Systems Architecture

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In the early 2000s, the superscalar CPU paradigm reached the point of diminishing returns mainly due to power requirements and overheating concerns. Faced with a constant demand for performance, hardware developers were in need of new ways to efficiently use the ever increasing transistor count predicted by Moore's law. The Chip MultiProcessors (CMPs) came as a natural solution to the power wall: several less complex and significantly less "power hungry" cores integrated on a single chip. In almost all ICT segments today, from High Performance Computing (HPC) to embedded devices, CMPs have become the architecture of choice. With this wide adoption of CMPs, software developers need to use parallel programming to fully exploit this architecture. Although parallelization can maximize the performance and energy efficiency of applications running on CMPs, it also comes with its own set of challenges. Among these, inherent management overheads that can account for sub-linear speedups and can increase the energy consumption of executions. Because of rising concerns for energy cost and battery life, much research and development today focuses on reducing power requirements and saving energy.In this thesis, we investigate how parallel programming can be used to improve the energy efficiency of applications running on CMP systems. We focus on a programming paradigm called Task Based Programming (TBP). The base concept of the TBP model is that the programmer focuses on identifying and annotating pieces of code (tasks) which can be executed concurrently with other tasks. An important result of our work is an increased understanding of how computations, parallelization and energy consumption relate when executing on CMP systems.Working in this direction, we use a simulation framework to allow for increased flexibility in design space exploration and noninvasive measurements. Unfortunately, the performance overhead of simulation is significant: simulating a parallel application can be 10000x slower than executing it on real hardware. In the first part of our research, we took it upon ourselves to try to solve this issue. We investigate the challenges of employing a sampling based technique to take advantage of the periodic behavior in TBP parallel applications. Our proposal is a simple 3-phase methodology that identifies only a small number of representative execution samples to simulate thus reducing the overall simulation time.In the second part of our work, we look at parallelization as a mean to save energy on CMP platforms. We test and compare two TBP libraries, Wool and Intel TBB, focusing on the behavior of some basic TBP parallelization operations like task spawning, task synchronization and task stealing. We investigate the energy footprint of these parallelization overheads and the effect it has on the energy-efficiency of the executing system. We have identified that failed task steals amount for the largest overhead. To reduce their impact and improve our system's energy efficiency, we devised a new occupa...

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Section: From Single-core To Multi-coresmentioning

confidence: 99%

Section: Evolution Of Cmpsmentioning

confidence: 99%

Tuning the victim selection policy of Intel TBB

Iordan

Jahre

Natvig

2015

Journal of Systems Architecture

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“…Current frequency scaling trends cannot be maintained due to numerous physical level issues. One major motivation for multi-core chips is the possibilities of this platform in managing the power consumption [15,24,27]. Due to the dramatic increase of power consumption and temperature it is not possible to optimize the power profile and thermal stability just by attacking the problems from device, interconnect or circuit levels.…”

Section: Implementation Of the Proposed Technique For Multi-core Powementioning

confidence: 99%

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, powergating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

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“…(2) Several research projects have proposed CMP architectures. (2,(35)(36)(37) In addition, commercial products have also been proposed (e.g., Intel Pentium D, AMD Athlon X2, IBM Power5, (38) and SUN Niagara (39) ).…”

Section: Related Workmentioning

confidence: 99%

“…This however, leads to an exponential increase at the gate level whereas getting the power consumption out of hand. (2) As such, major microprocessor manufacturers have shifted their strategy to multicore chips in order to avoid the memory and power walls.…”

Section: Introductionmentioning

confidence: 99%

A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model

Trancoso

Evripidou

Stavrou

et al. 2006

Int J Parallel Prog

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Current high-end microprocessors achieve high performance as a result of adding more features and therefore increasing complexity. This paper makes the case for a Chip-Multiprocessor based on the Data-Driven Multithreading (DDM-CMP) execution model in order to overcome the limitations of current design trends. Data-Driven Multithreading (DDM) is a multithreading model that effectively hides the communication delay and synchronization overheads. DDM-CMP avoids the complexity of other designs by combining simple commodity microprocessors with a small hardware overhead for thread scheduling and an interconnection network. Preliminary experimental results show that a DDM-CMP chip of the same hardware budget as a highend commercial microprocessor, clocked at the same frequency, achieves a speedup of up to 18.5 with a 78-81% power consumption of the commercial chip. Overall, the estimated results for the proposed DDM-CMP architecture show a significant benefit in terms of both speedup and power consumption making it an attractive architecture for future processors.

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The case for a single-chip multiprocessor

Cited by 131 publications

References 17 publications

Tuning the victim selection policy of Intel TBB

Tuning the victim selection policy of Intel TBB

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model

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