The Case for RISC-V in Space

Mascio, Stefano Di; Menicucci, A.; Furano, Gianluca; Monteleone, Claudio; Ottavi, Marco

doi:10.1007/978-3-030-11973-7_37

Cited by 21 publications

(16 citation statements)

References 7 publications

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“…1 Main CPU ISAs and their market share evolution in Europe and the United States (in bold SoCs). The figure is an updated version of the one contained in [7].…”

Section: Securitymentioning

confidence: 99%

“…An overview of the state-of-the-art of RISC-V was already given in [7]. Since then the state-of-the-art is evolving so quickly that a 1-year-old report on the state of the RISC-V toolset and on the IP cores available is already outdated (for instance, a big player like Western Digital recently announced that the code of their 32-bit 2-way superscalar RISC-V implementation will be soon available to the public [19] and many others could follow).…”

Section: Purpose Goal and Outlinementioning

confidence: 99%

“…The results reported in [17] confirm this approach also from a point of view of fault tolerance, as the behavior related to soft error can be predicted with an accurate estimation using results from a different implementation with the same ISA. Also, while the focus of [7] was on why using RISC-V in space applications, the goal of this work is to show how to employ RISC-V in space to enable new applications and improve satellite data system architectures. To do this, in Sec.…”

Section: Purpose Goal and Outlinementioning

confidence: 99%

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Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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“…1 Main CPU ISAs and their market share evolution in Europe and the United States (in bold SoCs). The figure is an updated version of the one contained in [7].…”

Section: Securitymentioning

confidence: 99%

Section: Purpose Goal and Outlinementioning

confidence: 99%

Section: Purpose Goal and Outlinementioning

confidence: 99%

See 1 more Smart Citation

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

Self Cite

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“…RISC-V's design is quite similar to the one of MIPS processor, having an optimized instruction set architecture (ISA) that aims at simplifying implementation. Although there were several soft-core implementations of RISC-V [4]- [12], and considering that the architecture has been evaluated for use in space applications [13], there are few fault-tolerant RISC-V processors.…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of a fault-tolerant RISC-V system-on-chip

Santos

Luza

Dilillo

et al. 2021

Microelectronics Reliability

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“…RISC-V allows developers to combine the advantages of both worlds [2], providing flexibility to both hardware and software.…”

Section: Introductionmentioning

confidence: 99%

Characterization of a RISC-V Microcontroller Through Fault Injection

Asciolla

Dilillo

Santos

et al. 2020

Lecture Notes in Electrical Engineering

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This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks.

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The Case for RISC-V in Space

Cited by 21 publications

References 7 publications

Leveraging the Openness and Modularity of RISC-V in Space

Leveraging the Openness and Modularity of RISC-V in Space

Reliability analysis of a fault-tolerant RISC-V system-on-chip

Characterization of a RISC-V Microcontroller Through Fault Injection

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