The design and optimization of SOC test solutions

Abstract

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Integrated test scheduling, test parallelization and TAM design

“…When referring to our technique, unless stated, the reported results are from using sorting based on an initial sorting of the test based on the key: t×p and our previous techniques are referred to as SA (Simulated Annealing) [3] and DATE [2]. For our approach a factor (f tam :f time ) is given to guide our algorithm depending on the importance of test time and TAM cost (see Section 5).…”

“…Our previous results referred to as DATE [2] and SA [3] were performed on a Sun Ultra Sparc 10 with 450 MHz processor and 256 Mb RAM [2,3]. To simplify the comparison we assume the two to be equal.…”

“…The advantage of the technique is its low computational cost making it useful for iteratively use in the early design space exploration phase. For extensive optimization for the final solution, we have proposed a technique based on Simulated Annealing, which is used only a few times justifying its high computational cost [3]. We have, independently, proposed an integrated test scheduling and scan chain partitioning (test parallelization) technique under power constraints [4].…”

An Integrated Framework for the Design and Optimization of SOC Test Solutions

“…The largest design is the Ericsson design [18,19] consisting of 8 DSP cores plus additional logic cores and memory banks, see Figure 19. Design characteristics are in Table 3 where the following notations are used:…”

“…The above set of tasks is performed in a single algorithm, which considers test conflicts, power limitation and test resource constraints [17,18,19]. The algorithm is suitable for early design space exploration due to its low computational complexity, which is an advantage since it will be used iteratively many times.…”