The design space layer: supporting early design space exploration for core-based designs

Peixoto, H.P.; Jacome, Margarida F.; Royo, A.; Lopez, J.C.

doi:10.1109/date.1999.761202

Cited by 3 publications

(3 citation statements)

References 8 publications

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“…We conceive the design space as a set of all feasible implementations of the domain model. The reuse library is an implementation of the design subspace [18]. The design space and concerns are the result of domain analysis.…”

Section: Explicit Mdsoc In Design Spacementioning

confidence: 99%

Soft IP Design Framework Using Metaprogramming Techniques

Štuikys¹,

Damaševičius²,

Ziberkas³

et al. 2002

Design and Analysis of Distributed Embedded Systems

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Abstract:We discuss the application of the metaprogramming techniques for soft IP design. Two metaprogramming paradigms are considered: the internal (using capabilities of the single language) and external (based on the usage of the target language and external metalanguage simultaneously) ones. The novelty of our approach is that we apply the concept of the multi-dimensional separation of concerns implemented via metaprogramming for the design of parameterized soft IPs for embedded systems in order to achieve higher flexibility, reusability and customizability.

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Section: Explicit Mdsoc In Design Spacementioning

confidence: 99%

Soft IP Design Framework Using Metaprogramming Techniques

Štuikys¹,

Damaševičius²,

Ziberkas³

et al. 2002

Design and Analysis of Distributed Embedded Systems

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“…17 We hope to help designers systematically consider relevant alternative implementations for SOC architecture's various components. This library layer also allows quick and transparent selection from reuse libraries of IP cores that are good candidates for implementing these components.…”

Section: Industry Initiatives and Standardization Effortsmentioning

confidence: 99%

A survey of digital design reuse

Jacome

Peixoto

2001

IEEE Des. Test. Comput.

Self Cite

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As integrated circuit technologies advance toward higher performance, greater densities, and increasing system complexity, CAD tools and design methodologies struggle to keep pace. Managing the formidable complexity of the design process is one of the main challenges to IC design. Disseminating design reuse is central to bringing the design effort's complexity back to a manageable size. Effective reuse, though, takes more than just gathering predesigned components in a library. Reuse-oriented policies and strategies must permeate the entire design process, from the methodologies themselves to the final designs.In this article, we provide a brief overview of the state of the art in design reuse for digital systems. We also discuss the challenges posed to this discipline by the recent trend toward integrating processor cores in high-volume application-specific integrated circuits.Design reuse, particularly in the core-based system-on-chip (SOC) design era, is no longer a discipline in isolation. Reuse cannot be fully separated from simulation and verification, estimation, synthesis, or test. For example, the "Design Section" of the 1999 edition of the International Technology Roadmap for Semiconductors emphasized the need for synthesis technology to support the reuse of predesigned General-purpose VHDL-based reuse Preis et al. proposed a domain-independent, VHDL-based reuse methodology for a hypertextbased reuse environment. 2 At the core of this A Survey of Digital Design Reuse Design Reuse 98 The authors survey recent advances in digital design reuse. They stress the need for effective strategies that accommodate reuse throughout the entire design process.

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“…Guerra et al [14] presented a design flow where the designer refines and improves the design by applying a series of optimizations. Peixoto et al [15] used a class hierarchy to represent available designs and relevant design decisions. In contrast to previous work, our framework permits us to explore a large parameterized processor design space in conjunction with a parameterized memory hierarchy design space efficiently.…”

Section: Related Workmentioning

confidence: 99%

Efficient design space exploration in PICO

Abraham

Rau

2000

Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems - CASES '00

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Automated design tools must understand and exploit the hierarchical structure of large design spaces. We have developed a general methodology for decomposing system design spaces into smaller component design spaces, followed by component-level evaluation, filtering, recomposition and system-level evaluation. This methodology greatly reduces the time and cost of design space exploration, since the typical number of system-level evaluations is greatly reduced. This paper describes the application of our decomposition methodology in the context of PICO. PICO is a design space exploration system that automatically generates embedded designs consisting of a stylized processor, hardware accelerator and a cache hierarchy, each customized to a benchmark.First, PICO splits the specified system design space into smaller design spaces, one for each of the components, viz. processor, accelerator and data/instruction/unified caches. PICO further partitions each component design space into predicated design spaces, so that all designs in a predicated design space satisfy a specified predicate. PICO uses component-level evaluations to identify the performance-cost optimal component-level Pareto designs in each predicated design space. PICO generates all compositions of Pareto designs from compatible predicated design spaces and uses a system-level evaluation to identify the Pareto designs at the system level. For reasonable design spaces, PICO reduces the design exploration time by over four orders of magnitude compared to an exhaustive approach.

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The design space layer: supporting early design space exploration for core-based designs

Cited by 3 publications

References 8 publications

Soft IP Design Framework Using Metaprogramming Techniques

Soft IP Design Framework Using Metaprogramming Techniques

A survey of digital design reuse

Efficient design space exploration in PICO

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