The driving force for development of IC and system in future: Reducing the power consumption and improving the ratio of performance to power consumption

A power-efficient and low-cost 1.0625-3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR's reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm 2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.

Section: Introductionmentioning

confidence: 99%

A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

Hou

Yang

Liu

et al. 2014

“…With the aggressive downscaling of device dimensions and the growing complexity of CMOS technology, variability has become a critical concern in the VLSI design and manufacturing [1][2][3][4][5][6][7][8][9]. The various variation sources can be categorized as systematic (global variations in lithography, etching, implant, etc.)…”

Section: Introductionmentioning

confidence: 99%

Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors

Wang

Huang

et al. 2013

Self Cite

Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects SCIENCE CHINA Information Sciences 57, 042404 (2014); Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs SCIENCE CHINA Information Sciences 62, 062404 (2019); A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors SCIENCE CHINA Information Sciences 61, 022401 (2018); Short channel carbon nanotube thin film transistors with high on/off ratio fabricated by two-step fringing field dielectrophoresis Science Bulletin 61, 794 (2016); On stress-induced voltage hysteresis in lithium ion batteries: Impacts of surface effects and interparticle compression SCIENCE CHINA Technological Sciences 62, 1357 (2019);. RESEARCH PAPER. SCIENCE CHINA Information Sciences

“…Considering both flexibility and energy efficiency, it is difficult to catch up with the rapid evolution of the multimedia market by relying on the ASIC, GPP, and programmable DSP solutions, or even a combination of these. Also, with the development of information technology and the arrival of the low-carbon economic era, integrated circuits (ICs) and systems that target high performance and low power consumption have widely penetrated all aspects of the national economy, national defense construction, and everyday life [4]. Nowadays, reconfigurable systems, which can perform computations in a specially designed reconfigurable processing unit (RPU) to greatly enhance performance and reduce power while retaining much of the flexibility, are becoming an attractive topic in the field of computing architecture.…”

Section: Introductionmentioning

confidence: 99%

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

Liu

Chen

Wang

et al. 2013

This paper proposes a task-based hybrid parallel and hybrid pipeline (THPHP) scheme to implement multi-standard video algorithms, including MPEG-2, H.264, and audio video coding standard (AVS), on a heterogeneous coarse-grained reconfigurable processor, called the reconfigurable multimedia system (REMUS). The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition (HD) video decoding standards. In THPHP, we propose both a task-based hybrid parallel scheme, in which macro-block (MB)-level, block-level, and sub-block-level decoding tasks are parallelized to improve data processing throughput, and a hybrid pipeline scheme, in which slice-level, MB-level, block-level and sub-block-level computations are pipelined to improve efficiency. Computation-intensive tasks, such as motion compensation, intra prediction, inverse discrete cosine transform, reconstruction, and deblocking filter, are implemented on two reconfigurable processing units, which are the core computing engines of REMUS. Thanks to the proposed schemes, the implementations can achieve H.264 high profile (HP) 1920×1080@30 fps streams, AVS Jizhun profile (JP) 1920×1080@39 fps streams, and MPEG-2 main profile (MP) 1920×1080@41 fps streams when working at 200 MHz frequency. Compared with XPP-III (a commercial reconfigurable processor), when implementing H.264 HD decoding, the performance and energy efficiency on REMUS are improved by 1.81× and 14.3×, respectively.