The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices

Abstract

This paper describes the architectural configuration of the Electrically Programmable Analog Circuit (EPAC™), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provides an overview of the technology and describes the internal operation of the first commercial EPAC devices. OverviewEPAC devices are analog ICs that can be programmed in functionality, interconnect, and performance characteristics. The EPAC device architecture is based on a mixed-signal CMOS process with on-chip SRAM and EEPROM memory to provide user programmability. Programming can be performed either off-line or in real-time. The SRAM components enable in-system functional reconfiguration, while leaving the original EEPROM configuration unchanged.EPAC technology raises the design task of system analog functions from a tedious and error-prone component level to a functional, or block, level. This is made possible by programmable analog "expert cell" modules each of which feature a variety of functions and performance characteristics. Using a PC-based development system, the user creates a circuit by selecting the functionality of the modules along with their respective performance settings and cell-to-cell interconnections.This approach greatly simplifies and shortens the design for analog circuits.Programmable analog devices offer significant benefits over traditional analog design approaches because they address key needs of today's system developers, by providing• High levels of integration • Instant prototyping and reprogramming • Design on block level using intuitive design tools • In-system reconfiguration for use in microcontrollerbased systems • No NRE for design or redesign • Minimum inventory and purchase commitment • Generalized test programs. The EPAC architecture also permits straightforward migration of designs to a compatible mask-programmable solution using a simpler process and smaller die size for highvolume applications. EECMOS Process TechnologyThe first implementation of EPAC technology is based on a 1.2 micron analog EECMOS process. This required adding a self-contained EEPROM process module (including a high-voltage generator) to a proven analog CMOS process without affecting the critical analog performance characteristics. This permits the device design engineers to draw from an existing library of high-performance cells, ranging from very fast circuits to high-precision converters, references, etc. This also ensures that the performance of the modules embedded in EPAC devices are competitive with dedicated ICs, while offering higher degrees of flexibility and functionality.

Design Approaches to Field-Programmable Analog Integrated Circuits

“…(Fig. 15), the ®rst IC in their series of Electrically Programmable Analog Circuit (EPAC) devices [13,32,77]. Aimed at multi-channel analog signal conditioning applications that require channel-dependent signal scaling and offsets, the 50E10 has an analog multiplexer front end, variable offset and gain modules, a summing ampli®er and output blocks that can be con®gured as comparators, ampli®ers or sample and hold circuits.…”

Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays

“…In 1995 IMP Inc. released a commercial FPAA-like product, the EPAC 50E10, and then released the EPAC 50E30 [Kle96]. Both are discrete-time designs based on switched-capacitor technology.…”

High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

“…In addition, the use of analog circuits would be made accessible to designers who do not have extensive expertise in the relevant subject, capitalizing on the FPAAs features. Therefore, the trend toward shorter design cycles and cheaper prices for analog integrated circuits has required the creation of various advances in the area of FPAA and related configurable analog blocks (CABs) [3]. These advancements have been necessary because of the nature of the field itself and the need to reach a commonly used widely acceptable CAB Structure.…”