The HTM Spatial Pooler—A Neocortical Algorithm for Online Sparse Distributed Coding

Cui, Yuwei; Ahmad, Subutai; Hawkins, Jeff

doi:10.3389/fncom.2017.00111

Cited by 89 publications

(35 citation statements)

References 70 publications

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“…The session can be first converted into the action ID sequence, and the ID will be In this paper, we will not discuss the details of the HTM model itself. For more information about the concepts, functions, and mathematical definitions used in the HTM, please see [13,[20][21][22][23][24].…”

Section: The Intrusion Scenario Discovery and Prediction Frameworkmentioning

confidence: 99%

Online Intrusion Scenario Discovery and Prediction Based on Hierarchical Temporal Memory (HTM)

Zhang

Fei

et al. 2020

Applied Sciences

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With the development of intrusion detection, a number of the intelligence algorithms (e.g., artificial neural networks) are introduced to enhance the performance of the intrusion detection systems. However, many intelligence algorithms should be trained before being used, and retrained regularly, which is not applicable for continuous online learning and analyzing. In this paper, a new online intrusion scenario discovery framework is proposed and the intelligence algorithm HTM (Hierarchical Temporal Memory) is employed to improve the performance of the online learning ability of the system. The proposed framework can discover and model intrusion scenarios, and the constructed model keeps evolving with the variance of the data. Additionally, a series of data preprocessing methods are introduced to enhance its adaptability to the noisy and twisted data. The experimental results show that the framework is effective in intrusion scenario discovery, and the discovered scenario is more concise and accurate than our previous work.

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Section: The Intrusion Scenario Discovery and Prediction Frameworkmentioning

confidence: 99%

Online Intrusion Scenario Discovery and Prediction Based on Hierarchical Temporal Memory (HTM)

Zhang

Fei

et al. 2020

Applied Sciences

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“…More importantly, a device failure in the crossbar RRAM array causes significant performance degradation in the neuromorphic systems 24 , 25 . Among the various neuromorphic architectures, the crossbar array can be served as a spatial pooler (SP) for hierarchical temporal memory (HTM) that describes the functionality of the human neocortex 26 , as shown in Fig. 1 .…”

Section: Introductionmentioning

confidence: 99%

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

Woo

Nguyen

Kim

et al. 2020

Sci Rep

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A crossbar array architecture employing resistive switching memory (RRAM) as a synaptic element accelerates vector-matrix multiplication in a parallel fashion, enabling energy-efficient pattern recognition. to implement the function of the synapse in the RRAM, multilevel resistance states are required. More importantly, a large on/off ratio of the RRAM should be preferentially obtained to ensure a reasonable margin between each state taking into account the inevitable variability caused by the inherent switching mechanism. The on/off ratio is basically adjusted in two ways by modulating measurement conditions such as compliance current or voltage pulses modulation. the latter technique is not only more suitable for practical systems, but also can achieve multiple states in low current range. However, at the expense of applying a high negative voltage aimed at enlarging the on/off ratio, a breakdown of the RRAM occurs unexpectedly. This stuck-at-short fault of the RRAM adversely affects the recognition process based on reading and judging each column current changed by the multiplication of the input voltage and resistance of the RRAM in the array, degrading the accuracy. to address this challenge, we introduce a boost-factor adjustment technique as a faulttolerant scheme based on simple circuitry that eliminates the additional process to identify specific locations of the failed RRAMs in the array. Spectre circuit simulation is performed to verify the effect of the scheme on Modified National Institute of Standards and Technology dataset using convolutional neural networks in non-ideal crossbar arrays, where experimentally observed imperfective RRAMs are configured. Our results show that the recognition accuracy can be maintained similar to the ideal case because the interruption of the failure is suppressed by the scheme.

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“…As a software framework for modeling the neocortical function, Hierarchical Temporal Memory (HTM) has been developed recently [15,16,17,18,19,20]. Figure 1a shows a functional block diagram of HTM that is composed of the Spatial Pooler (SP) and Temporal Memory (TM).…”

Section: Introductionmentioning

confidence: 99%

“…SP receives the sensory information to learn the cortical representation. As a result, SP generates Sparse Distributed Representation (SDR) [16]. SDR is a mathematical description for representing the cortical neurons that may be activated or deactivated in response to the sensory information from the cochlea, retina, etc.…”

Section: Introductionmentioning

confidence: 99%

“…SDR is a mathematical description for representing the cortical neurons that may be activated or deactivated in response to the sensory information from the cochlea, retina, etc. Actually, SP was proposed as a software algorithm in the HTM software framework [15,16,17,18,19,20]. To realize the spatial pooling with hardware, we developed the spatial-pooling memristor crossbar circuit in a previous work, where the circuit could convert the sensory information to the SDR that meant the representation of cortical neurons [21].…”

Section: Introductionmentioning

confidence: 99%

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Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons

Nguyen

Pham

2019

Materials

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As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain’s neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit its architectural benefit. To do so, we propose a new memristor-CMOS (Complementary Metal-Oxide-Semiconductor) hybrid circuit of temporal-pooling here, which is composed of the input-layer and output-layer neurons mimicking the neocortex. In the hybrid circuit, the input-layer neurons have the proximal and basal/distal dendrites to combine sensory information with the temporal/location information from the brain’s hippocampus. Using the same crossbar architecture, the output-layer neurons can perform a prediction by integrating the temporal information on the basal/distal dendrites. For training the proposed circuit, we used only simple Hebbian learning, not the complicated backpropagation algorithm. Due to the simple hardware of Hebbian learning, the proposed hybrid circuit can be very suitable to online learning. The proposed memristor-CMOS hybrid circuit has been verified by the circuit simulation using the real memristor model. The proposed circuit has been verified to predict both the ordinal and out-of-order sequences. In addition, the proposed circuit has been tested with the external noise and memristance variation.

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The HTM Spatial Pooler—A Neocortical Algorithm for Online Sparse Distributed Coding

Cited by 89 publications

References 70 publications

Online Intrusion Scenario Discovery and Prediction Based on Hierarchical Temporal Memory (HTM)

Online Intrusion Scenario Discovery and Prediction Based on Hierarchical Temporal Memory (HTM)

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons

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