The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling

Abstract

The System/360 Model 91 central processing unit provides internal computational performance one to two orders of magnitude greater than that of the IBM 7090 Data Processing System through a combination of advancements in machine organization, circuit design, and hardware packaging. The circuits employed will switch at speeds of less than 3 nsec, and the circuit environment is such that delay is approximately 5 usee per circuit level. Organizationally, primary emphasis is placed on (1) alleviating the disparity between storage time and circuit speed, and (2) the development of high speed floating-point arithmetic algorithms.This paper deals mainly with item (1) of the organization. A design is described which improves the ratio of storage bandwidth and access time to cycle time through the use of storage interleaving and CPU buffer registers. It is shown that history recording (the retention of complete instruction loops in the CPU) reduces the need to exercise storage, and that sophisticated employment of buffering techniques has reduced the effective access time. The system is organized so that execution hardware is separated from the instruction unit; the resulting smaller, semiautonomous "packages" improve intra-area communication.

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

“…Out-of-order execution relaxes this ordering constraint, thereby increasing concurrency [2], [63], [64].…”

“…Another option is to have a combined storage space, a physical register file, and use register mapping tables to determine which physical registers contain architectural values, and which contain nonarchitectural value. This requires a scheme for register renaming [2], [17], [25], which we discuss next.…”

“…Register renaming was originally proposed to facilitate out-of-order execution, by overcoming artificial dependence constraints for a machine with a limited number of registers [2], [64]. Today, it is used to also facilitate speculative execution.…”

“…Many of these applications exhibit fairly regular array accesses often accessing elements in a linear fashion (e.g., a [1], a [2], a [3] and so on), a program behavior that can be exploited. Stream buffers are hardware mechanisms that identify and exploit such access patterns to reduce memory latency [24].…”

Algebraic Models of Superscalar Microprocessor Implementations: a Case Study

“…Machines capable of parallel instruction execution have existed since the 1960s. For example, the CDC 6600 ), and the IBM 360/91 (Anderson et al [1967]). These machines were not superscalar, though they did contain parallel functional units: necessary because of the advanced pipelining techniques they used.…”