The kill rule for multicore

Abstract

Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore's Law for multicore, we expect to see 1K multicore chips within a decade. 1K multicore systems introduce significant architectural challenges. One of these is the power efficiency challenge. Today's cores consume 10's of watts. Even at about one watt per core, a 1K-core chip would need to dissipate 1K watts! This paper discusses the "Kill rule for multicore" for power-efficient multicore design, an approach inspired by the "Kiss rule for RISC processor design". Kill stands for Kill if less than linear, and represents a design approach in which any additional area allocated to a resource within a core, such as a cache, is carefully traded off against using the area for additional cores. The Kill Rule states that we must increase resource size (for example, cache size) only if for every 1% increase in core area there is at least a 1% increase in core performance.

Branch penalty reduction on IBM cell SPUs via software branch hinting

“…With the total power budget capped, more cores can only be added by reducing the power and the complexity of each core [9,11]. Consequently, architects started looking at processor components that could be removed to simplify the cores, yet not lose too much on performance [3]. In the power-efficient IBM Cell Synergistic Processing Units (SPUs) [17], jointly developed by Sony, Toshiba, and IBM, architects decided to remove hardware branch predictor and used software branch hinting in the hope to recover lost performance [22].…”

Fonksi̇yonel Programlama Di̇lleri̇ İle Paralel Programlama

“…Kill if Less Than Linear) kuralıdır [4]. Bu prensip günümüzde bazı çok çekirdekli işlemcilerin tasarımına öncülük etmektedir [5].…”

On Modeling the Lifetime Reliability of Homogeneous Manycore Systems

“…A 128-core GPU [15] and a 64-core general-purpose multiprocessor [22] have already been released to the market. Various research teams have projected that thousand-core processor chips will become commercially available in the foreseeable future [1,4]. For such largescale manycore systems fabricated with latest technology, how to model its lifetime reliability is an interesting and relevant problem.…”