The picoArray and reconfigurable baseband processing for wireless basestations

In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programmability, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multipledata datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the singleinstruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.

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“…The PEs are usually connected together through a reconfigurable fabric. Processors that fall into this category are [20][19] [3].…”

Section: Related Workmentioning

confidence: 99%

AnySP: Anytime Anywhere Anyway Signal Processing

et al. 2010

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“…However, there is no work that tries to justify which processor core architecture is the best for those platforms. PicoArray from picoChip [1] uses more than 300 3-issue VLIW cores with a 16-bit datapath. The Tile64 platform from Tilera, based on the RAW research platform [7], has 64 32-bit 3-issue VLIW cores.…”

Section: Related Workmentioning

confidence: 99%

“…At present, those platforms use up to several hundred processor cores [1,2]. Those cores are typically RISC architectures, having single or multiple issues like VLIW processors.…”

Section: Introductionmentioning

confidence: 99%

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

Rousseau

Manet

Loiselle

et al. 2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.

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