The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era

Abstract

In this paper, we present the Prism Bridge, a soft IP core developed to bridge FPGA-MPSoC systems using high-speed serial links. Considering the current trend of ubiquitous serial transceivers with staggeringly increasing line rates, minimizing overhead and maximizing data throughput becomes paramount. Hence, our main design goal is to maximize bandwidth utilization for AXI data, which we realize through an advanced packetization mechanism. We give an overview of the Prism Bridge's design and analyze its half-duplex bandwidth utilization. Additionally, we discuss the results of the experiments we conducted to assess its real-world performance, including measurements of throughput and latency of various combinations of line rates, link-layer cores, and bridge cores. Using a serial link with a 16.375 Gbit/s line rate, the Prism Bridge with an advanced packetizing mechanism achieved an AXI write throughput of 1368.82 MiB/s and an AXI read throughput of 1376.62 MiB/s, an increase of 46.20% and 45.86%, respectively, compared with the de-facto industry-standard core. The advanced packetization mechanism had negligible impact on latency but required 69.15%-73.91% more LUTs and 33.62%-36.19% more flipflops. We conclude that for most designs that support inter-chip AXI transactions and will not be limited to short transaction lengths, the higher data throughput of the Prism Bridge with an advanced packetization mechanism is worth its cost in additional logic resource utilization.INDEX TERMS Cluster computing, computer architecture, field-programmable gate arrays, high-speed serial, inter-chip axi communication, protocols. LIST OF SYMBOLSLength of an AXI transaction in transfers (i.e., AxLEN + 1). m ∈ N Number of Hamming code and parity bits per word of n data bits. n ∈ N AXI-Stream data width. R