The Use of Computer Simulation in the Electronic Packaging Process

Abstract

This paper deals with the use of the computer simulation for semiconductor chip attach investigation, where the wire bonding is the mostly used process. The main focus lays on the correct definition of the capillary trace, which is essential for creation of a good bond contact as for chip, as well for package or substrate pad. Several simulations for different shapes of loops were created and compared with real bonds, which were done based on the settings from the analysis.