Thermal Performance of 3D IC Package with Embedded TSVs

Abstract

more than two chips and these IC chips can be stacked up vertically and communicate with each other through vias.However, thermal challenge of the 3D IC chip stack becomes a limitation for using the TSVs because the heat spreading in the stack is less effective than non-stacked chips. [4,5] Therefore, thermal performance is the major concern for vertical IC chip stack. TSV is a metal-filled component embedded in a silicon chip, where a dielectric layer (e.g. silicon dioxide, SiO 2 ) is deposited between the bulk silicon and the metal filling. The thermal conductivity of SiO2 layer is orders of magnitude less than that of metal filling, e.g. the copper. Thus, the thermal property for a TSV or a TSV group is much better in vertical direction than in the planar direction.Thermal solutions for stacked IC structure have been proposed and investigated from literature. [6,7] Experiment results and simulation analyses have also been reported, especially for the TSV thermal behavior. [4,5,8,9] Oprins et al. [8] has designed and fabricated a test chip as well as conducted the measurements of thermal performance for the test vehicle, which one thinned chip with TSV is bonded on top of a thick chip without TSV using Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 31040, Taiwan (Received July 23, 2012; accepted November 5, 2012) Abstract A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement of thermal resistance from junction to the package case surface (bottom). The thermal resistances for the layers of chips, micro bumps, underfill resin between chips, and ceramic substrate are also being analyzed with the thermal RC model theory and the cumulative structure function. The top chip is embedded with through-silicon vias (TSVs) and is thinned down to 60 μm thick. The bottom chip has no TSV and the thickness is the same as a normal IC chip. Both chips have the same layout and include two types of heaters. The first heater is designed to emulate a hot spot and is located at the chip center. The second heater, with heat flux level (uniform heating) close to 1/20 of the first heater, is designed to heat up the surrounding area of the first heater. A simulation model of the QFP package is developed and a set of equivalent thermal conductivity correlations in planar (xy) and vertical (z) directions of TSVs are used in order to simplify the simulation model and shorten the computational time. Comparisons between simulation models show that the result is accurate for uniform heating condition and satisfactory for hot spot heating condition.Keywords: 3D IC, Through Silicon Via, Chip Stacking, Thermal Conductivity, QFP Package 76Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012 analysis in design phases. Lau and Yue[9] studied the equivalent thermal conductivities in planar and vertical directions for 3D IC structure with TSVs embedded in stacked chips in simulations. The simulation results of equivalent thermal conducti...