Third Party CAD Tools for FPGA Design—A Survey of the Current Landscape

Nelson, Brent

doi:10.1007/978-3-030-17227-5_25

Cited by 3 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several third-party CAD tools have been developed over the years, with some primarily being used for experimentation on hypothetical FPGAs, such as Verilog-to-Routing (VTR) [7], and others targeting commercial FPGAs. The tools that target commercial FPGAs fit within two main categories: (1) Cooperative CAD Tool Frameworks and (2) Stand-alone, Vendor-independent tools [26].…”

Section: Third-party Cad Tools and Related Workmentioning

confidence: 99%

Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

Glick

Grigg

Nelson

et al. 2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

Circuit designs for field-programmable gate arrays (FPGAs) are typically compiled by FPGA vendor tools, such as Xilinx's Vivado Design Suite. In recent years, partial reconfiguration (PR) has emerged as a popular technique that allows portions of an FPGA to be dynamically reconfigured after the complete device has been configured with an initial bitstream. However, the nature of current FPGA vendor tools limits further innovation and possible usage models of PR. This thesis presentsMaverick, an open-source proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target PR regions in FPGA designs. Maverick builds upon existing open source tools (Yosys [1], RapidSmith2 [2], and Project X-Ray [3]) to form an end-to-end compilation flow. After an initial static design and PR region are created with Xilinx's Vivado PR flow, Maverick can then compile and configure RMs onto that PR region-without the use of vendor tools. In addition, this work enables users to import and export RMs between Vivado and RapidSmith2.Furthermore, this thesis demonstrates Maverick compiling RMs on both a desktop computer and on the embedded PYNQ-Z1 board, which contains a Zynq 7020 system on chip (SoC). Maverick runs on the ARM processor embedded within the processing system (PS) of the Zynq device, generating partial bitstreams which can then be configured onto a PR region within the programmable logic (PL) fabric of the same Zynq device. This unique case, not possible with current vendor tools like Vivado, demonstrates the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

show abstract

Section: Third-party Cad Tools and Related Workmentioning

confidence: 99%