Three-dimensional SRAM design with on-chip access time measurement

Abstract

An SRAM design in a 3D 0.18 mm silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32% improvement in the access time is gained by using 3D technology.Introduction: Three-dimensional integrated circuit (3D IC) technologies have demonstrated potential for improving the performance of digital systems [1]. They have the benefits of shorting the wire length from a 2D system and providing massive interconnect bandwidth between stacking dies. Previous research in 3D SRAM design [2][3][4] has shown the potential of access time reduction. However, previous work is mostly based on theoretical analyses and modelling, and does not show a physical implementation. To validate the benefits of 3D technology and measure the variations among tiers, in the work reported in this Letter, an SRAM array was designed and fabricated in the MIT Lincoln Lab (LL) 0.18 mm 3D silicon-on-insulator (SOI) process [5]. The circuit was built on three tiers and connected by through-siliconvias (TSVs). The cross-section of the die stacking is shown in Fig. 1.