Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors During Pulse Operation

Abstract

The threshold voltage shift of amorphous silicon thin film transistors (TFT's) under pulse operation is discussed. The stress time, stress voltage, duty ratio and frequency dependence of the shift have been measured. A positive voltage stress causes a constant shift, when the frequency is in the range from DC to over 100 kHz. On the other hand, the shift under a negative pulse stress depends on its repetition frequency and its pulse width and can be described by an equivalent circuit model. Based on these data, a more reliable estimate of the long-term reliability of an amorphous silicon TFT panel has been realized.

The Instability Mechanisms of Hydrogenated Amorphous Silicon Thin Film Transistors under AC Bias Stress

“…However, up to this date, the reliability of a-Si:H TFTs under AC bias stress [13][14][15][16][17] have been paid little attention. In practice, the a-Si:H TFTs used as switching elements for active-matrix liquid-crystal displays (AMLCDs) are operated in an AC mode.…”

Photon Detectors

“…[55,56] If the ∆V T data for negative stress voltages are plotted with respect to gatestress voltage, V ST , we notice a value of around 2.49 for the term a, as shown in Powell claimed that defect-state reduction is responsible for the ∆V T at low negative voltages, but there might be some charge-trapping effects as the stress voltage becomes more negative. [55,56] If the ∆V T data for negative stress voltages are plotted with respect to gatestress voltage, V ST , we notice a value of around 2.49 for the term a, as shown in Powell claimed that defect-state reduction is responsible for the ∆V T at low negative voltages, but there might be some charge-trapping effects as the stress voltage becomes more negative.…”

“…With respect to the results in Fig. In practice, when TFT ON and OFF periods are comparable, the a-Si TFTs used in the AMLCD industry [55,56] require bipolar gate pulses for long-term ∆V T management. However, ∆V T appears to have a power law dependence on both gate bias and stress time.…”

“…In-house 2.5 0.28 Kanicki [55] 2.4 0.32 Tsukada [56] 3.8 0.25 Figure 6.21 ∆V T for a bipolar pulse and its two unipolar components.…”

Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

“…High electrical stability is a key requirement for a-Si TFTs. Many studies, however, clarified that device threshold voltage (V th ) degrades with gate bias (V g ) stress due to charge trapping and/or defect state creation (including tail states and deep states) [2][3][4][5][6][7][8][9][10][11]. Depending on stress polarity, charge trapping produces either positive or negative parallel shift in the transfer characteristic.…”