Time-interleaved pipelined ADC design for computational intelligence and cloud computing application

Lai, Wen Cheng; Huang, Jhin Fang; Lin, Wey Jinq; Chiu, Ta Chen

doi:10.1109/ccis.2014.7175811

2014 IEEE 3rd International Conference on Cloud Computing and Intelligence Systems 2014

DOI: 10.1109/ccis.2014.7175811

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Time-interleaved pipelined ADC design for computational intelligence and cloud computing application

Wen Cheng Lai

Jhin Fang Huang

Wey Jinq Lin

et al.

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2020

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“…Time-interleaved analog-to-digital converters (TI-ADCs) [1] are widely used in many high-speed applications, such as communications [2][3][4], oscilloscopes [5][6][7] and healthcare instruments [8][9][10]. A TI-ADC uses several sub-analog-to-digital converters (sub-ADCs) to obtain a high sampling rate.…”

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Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

Cao

Liu

et al. 2020

J. Inst.

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A time-interleaved analog-to-digital converter (TI-ADC) uses several sub-analog-todigital converters (sub-ADCs) to achieve a high sampling rate. Its applications include communication systems, oscilloscopes, healthcare instruments, etc. However, the presence of sub-ADC channel mismatches such as offset, gain and sample-time mismatches can significantly degrade the performance of TI-ADCs. This paper proposes a fully digital foreground calibration technique for the TI-ADC, including mismatch correction and estimation blocks. Unlike existing techniques, the proposed technique requires low computational resources. As the resource for complex computing in a field-programmable gate array (FPGA) is mainly the digital signal processor (DSP), the mismatch correction block unifies each computing unit in the FPGA into a multiply adder to achieve low DSP consumption. To further reduce the use of DSP resources, the selection of an optimal number of taps of the finite impulse response filter used for mismatch correction is discussed. The optimal-tap filter that uses the lowest amount of DSPs while satisfying the required signal-to-noise and distortion ratio flat area bandwidth is presented. A real-time hardware correction block was implemented for an 8 Gs/s TI-ADC system with two sub-ADC channels, and the results with this hardware verify the low computing resource consumption feature of the proposed calibration technique.

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confidence: 99%

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

Cao

Liu

et al. 2020

J. Inst.

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Time-interleaved pipelined ADC design for computational intelligence and cloud computing application

Cited by 1 publication

References 33 publications

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

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