Total-Dose Worst-Case Test Vectors for Leakage Current Failure Induced in Sequential Circuits of Cell-Based ASICs

Worst-case test vectors of sequential ASiCS exposed to total dose

“…In this methodology, we target both logic failures and leakage current failures induced by total dose. This methodology depends on the cell-level fault models we developed in previous effort for both total dose induced logic and leakage current failures [1]- [4]. The block diagram in Figure 1 represents an example for a cycle-free sequential Worst-Case Test Vectors of Sequential ASICs Exposed to Total Dose Ahmed A. Abou-Auf, Mostafa M. Abdel-Aziz, Hamzah A. Abdel-Aziz and Amr G. Wassal T circuit is a 4-stage pipelined 5x5 multiplier where every stage has a combinational circuit followed by a register.…”

“…However, they are typically not used in total-dose testing of ASIC devices because they are known to be almost impossible to identify for most VLSI devices. We have developed couple of methodologies to identify WCTV for both logic failures and leakage-current failures induced by total ionizing dose (TID) in standard-cell ASICs [1]- [3]. Those methodologies follow the typical design flow of ASIC devices using standard cell library.…”

“…Therefore, worst-case test vectors become a sequence of test vectors. In previous effort [1], we have used an exhaustive search to identify worst-case test vectors in sequential circuits which is by definition limited to circuits with small number of inputs and states. In this paper, we introduce a novel methodology to make the identification of worst-case test vectors in any size of synchronous sequential circuits for ASICs devices.…”