2014 Ieee Region 10 Symposium 2014
DOI: 10.1109/tenconspring.2014.6863068
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Towards a RISC instruction set architecture for the 32-bit VLIW DSP processor core

Khoi-Nguyen Le-Huu
1
,
Diem Ho
2
,
Anh-Vu Dinh-Duc
3
et al.
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Cited by 4 publications
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References 9 publications
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Design and Implementation of Configurable SHIFT Instructions Targeted at Symmetrical Cipher Processing

Liu
1
,
Zeng
2
,
Li
3
et al. 2017
Procedia Computer Science
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Design and Implementation of Configurable SHIFT Instructions Targeted at Symmetrical Cipher Processing

Liu
1
,
Zeng
2
,
Li
3
et al. 2017
Procedia Computer Science
0
0
0
0
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A micro-architecture design for the 32-bit VLIW DSP processor core

Le-Huu
1
,
Dinh-Duc
2
,
Nguyen
3
2014
The 20th Asia-Pacific Conference on Communication (APCC2014)
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RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core

Le-Huu1,
Dinh-Duc2,
Dang-Do
3
et al. 2014
2014 International Conference on Advanced Technologies for Communications (ATC 2014)
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