Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM

Abstract

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications.