Towards high performance network-on-chip: A survey on enabling technologies, open issues and challenges

Phing, Ng Yen; Warip, Mohd Nazri Mohd; Ehkan, Phaklen; Ahmad, Robiah; Zakaria, Fazrul Faiz; Zulkefli, F. W.

doi:10.1109/iced.2016.7804649

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…This increases the significance of implementing a reliable and highly efficient communication architecture that takes sufficient care of these packets unless delivered. For such communication-intensive architectures, traditional communication methodologies such as bus-based interconnection or point-to-point interconnection becomes less feasible because of lack of proper scalability (Shahane and Pisharoty, 2019) and performance improvement chances (Phing et al, 2016;Debbarma and Debbarma, 2017). Analyzing the requirements of such advanced systems, a high performance, reusable and scalable NoC can be a promising solution (Jain et al, 2015).…”

Section: Introductionmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

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Purpose This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter. Design/methodology/approach The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation. Findings According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter. Originality/value This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

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Section: Introductionmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

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“…In recent year, there are several research paper about the basic issue and traditional challenges of Network-on-Chip (NoC) [1]. The performance such as low power consumption, low area, low latency, and high throughput are the main desirable characteristic for NoC architecture.…”

Section: Introductionmentioning

confidence: 99%

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

Phing¹,

Warip²,

Ehkan³

et al. 2018

IJEECS

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<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

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