Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

Chen, Changlin; Fu, Yanwei; Cotofana, Sorin

doi:10.1109/tcad.2016.2570680

Cited by 4 publications

(8 citation statements)

References 35 publications

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“…The studies in [18][19][20] dealt with transient faults that were due to crosstalk. In [24][25][26], the authors investigated the problem of short and open circuit faults in the links of an NoC. In [27][28][29], the authors discussed the yield of vertical links in 3D NoCs.…”

Section: Fault Tolerance and Network-on-chipmentioning

confidence: 99%

“…Some studies have employed techniques related to flow control, such as bus encoding [18], retransmission [20], and bandwidth allocation [49]. Others have adopted additional links, such as the duplication of wires and channels [24,50], spare links [41,51], link serialization [26], or by generating new links [25]. The main focus in 3D NoCs is on the TSVs and the problems related to the manufacturing process [27,29].…”

Section: Network-on-chip Layersmentioning

confidence: 99%

“…It is usually implemented by running an algorithm n times on the same hardware. In NoCs, some works employ temporal redundancy through the generation of multiple sampling of a message [19,32,48] or through link sections [26].…”

Section: Detection and Correctionmentioning

confidence: 99%

“…In BIST, specific hardware generates stimuli at the inputs of a circuit and compares the output with the correct expected values. Variations of this technique were employed in NoCs [24,26,34,41,45].…”

Section: Diagnosis and Repairmentioning

confidence: 99%

“…After discovering a defective component, it is desirable to disable it and implement a contingency plan, such as reconfiguration, before resuming the execution. In routers, it is possible to employ techniques that can avoid faulty components in the switching logic [21], arbiters [52], and links [26]. However, the focal point of the research is on the reconfiguration of the routing tables, as well as the algorithms needed to bypass faulty routers [28,[40][41][42][43]47,55].…”

Section: Diagnosis and Repairmentioning

confidence: 99%

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Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design

Melo

Zeferino

Dilillo

et al. 2019

Sensors

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Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.

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