Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Abstract

CITATIONS 0 READS 22 4 authors, including: Some of the authors of this publication are also working on these related projects: 3Ccar -Integrated Components for Complexity Control in affordable electrified cars View project SAFEPOWER -Safe and secure mixed-criticality systems with low power requirements View project Maher Fakih OFFIS e.V. ABSTRACTScenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability. On the one side, they support the timing analysis of real-time applications, especially those running on MPSoCs, due to the clean separation of computation and communication phases in their executing nodes. On the other side, SADFGs allow the expression of a more dynamic behaviors than Synchronous dataflow graphs by allowing dynamic token-rates of single nodes depending on pre-defined typical scenarios. The fact which leads to more efficiency and better throughput.In this paper, we describe the extension of a previous model-checking based real-time analysis approach to allow the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multiprocessor architecture. We demonstrate our approach on an MPEG decoder application being viable to obtain the worst-case end-to-end latency of its implementation under different scenarios on a 2-tiles MPSoC.