Trace-driven workload simulation method for Multiprocessor System-On-Chips

Isshiki, Takaaki; Li, Dongju; Kunieda, Hiroaki; Isomura, Toshio; Satou, Kazuo

doi:10.1145/1629911.1629975

Cited by 18 publications

(26 citation statements)

References 16 publications

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“…This assumption complies well with a workload simulation technique for example as presented in Ref. [8]. The estimation technique works such that, for an arbitrary window of "T" cycles, histograms on all busworkloads and computational-workloads on each PE for a given application are provided to the prediction model which calculates the bus contention stall for each PE.…”

Section: Introductionmentioning

confidence: 77%

“…Although the model can be used with any schedule aware simulator where the computational and bus workloads on each PE are known, we use our bus model as an addition to the trace driven workload simulator presented in Ref. [8]. Figure 1 shows an overview of the performance estimation flow in a trace driven workload simulation.…”

Section: Overview Of Proposed Simulation Flowmentioning

confidence: 99%

“…In the trace simulator presented in Ref. [8] a Program Trace Graph (PTG) is used for efficient trace retrieval. The PTG consists of nodes and edges such that each PTG-node represents function-start, function-end, branch or call.…”

Section: Arbitration Simulation Technique In a Trace Simulatormentioning

confidence: 99%

See 2 more Smart Citations

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

Shafiq

Isshiki

2017

IPSJ Transactions on System LSI Design Methodology

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Accurate and fast performance estimation methods for modern and future multi-core systems are the focal point of much research due to the complexity associated with such architectures. The communication architecture of such systems has a huge impact on the performance and power of the whole system. Architects need to explore many design possibilities by using performance estimation techniques at early stages of design to make design decisions earlier in the design cycle. While software developers need to develop and test applications for the target architecture and gather performance measurements as early in the design cycle as possible. Full system simulation techniques provide accurate performance values but are extremely time consuming. Static analysis techniques are fast but cannot capture the dynamic behavior associated with shared resource contention and arbitration. Moreover, synthetic traffic patterns have been used to analyze the communication architecture however, such patterns are not realistic enough. We propose a statistical based model to predict the dynamic cost of bus arbitration on the performance of a bus architecture. The proposed model uses workload trace of the actual applications and benchmarks to capture the real application traffic behavior. Statistics on the traffic patterns are collected and input to the analytical model which calculates performance values for the communication architecture under consideration. By knowing the performance measures, designers can avoid over and under-design of the communication architecture. This paper builds up on a previously developed performance estimation model. The previous work modeled single and burst bus-transfers, however only one interfering bus master at a time for each blocked bus request was considered. The proposed, improved accuracy model considers multiple interfering masters for each blocked request hence improving the estimation accuracy especially for traffic intensive applications and many PE architectures. Experiments are performed for two different architectures i.e., 4 processing elements connected via a shared bus and 8 processing elements connected via a shared bus. Results show no significant difference in accuracy compared to previously developed model, for low traffic applications SPARSE and ROBOT however notable accuracy improvement for traffic intensive applications. Maximum estimation error is reduced from 1.75% to 0.6% for FPPPP and from maximum 13.91% to 8.8% for FFT on the 4PE architecture. On the 8PE architecture, maximum estimation error is reduced from 11.8% to 2.7% for the FPPP benchmark. Moreover simulation speed-up for the proposed technique over simulation method is reported.

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Section: Introductionmentioning

confidence: 77%

Section: Overview Of Proposed Simulation Flowmentioning

confidence: 99%

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An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

Shafiq

Isshiki

2017

IPSJ Transactions on System LSI Design Methodology

Self Cite

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“…All of the above assumptions are common in the literature and have been widely used by different researchers [2,22,23,33,34].…”

Section: Assumptionsmentioning

confidence: 99%

Flattening: An efficient approach to improving the performance of conventional MINs

Rezazadeh

Safaei

Moazez³

2015

Microelectronics Journal

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“…Therefore, for rapid performance evaluations, MPSoC components should be modeled at a higher level of abstraction. As a trade-off between accuracy and performance, trace-based approaches have been proposed [1], [2], [3], [4], [5]. Traces capture the software execution in abstract form and, thus, accelerate the exploration of MPSoC architectures.…”

Section: Introductionmentioning

confidence: 99%

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

Plyaskin

Masrur

Geier

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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Due to the growing complexity of multiprocessor systems-on-chip (MPSoCs), there is an increasing demand on efficient design space exploration techniques. In addition to the analysis of diverse hardware architectures, these techniques should assist the designer in the flexible evaluation of various scheduling policies and application mappings while taking effects of the shared on-chip communication infrastructure into account. Most available simulation approaches are either unable to cover all these aspects jointly or have poor simulation performance. In this paper, we present a framework for timing analysis of MPSoC architectures using abstract and yet accurate traces. The traces capture both precise processing latencies and memory access patterns and represent application-and OS-related workload. Performance estimation is performed by an interleaved execution of the traces on a highly configurable multiprocessor platform modeled in our trace-driven SystemC TLM simulator. Using the flexible scheduler model presented in this paper, various mappings and scheduling policies can be rapidly evaluated while considering on-chip interconnect contention and usage of shared resources. Due to the abstraction of the trace-driven simulations, the proposed framework allows for both fast and accurate explorations of MPSoC design alternatives.

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Trace-driven workload simulation method for Multiprocessor System-On-Chips

Cited by 18 publications

References 16 publications

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

Flattening: An efficient approach to improving the performance of conventional MINs

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

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