Trap Characterization in InAlN/GaN and AlN/GaN based HEMTs with Fe- and C-doped Buffers

Dupouy, Emmanuel; Raja, P. Vigneshwara; Gaillard, Florent; Sommet, Raphaël; Nallatamby, Jean-Christophe

doi:10.23919/eumic50153.2022.9783939

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…The drain current transient (DCT) test involves applying large positive V ds bias, large negative V gs bias, or both to measure the change in I DS [48][49][50][51][52][53][54][55][56]. The transient current I DS can be expressed as…”

Section: Drain Current Transientmentioning

confidence: 99%

Trap Characterization Techniques for GaN-Based HEMTs: A Critical Review

Zou,

Yang,

Qiao

et al. 2023

Micromachines

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Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have been considered promising candidates for power devices due to their superior advantages of high current density, high breakdown voltage, high power density, and high-frequency operations. However, the development of GaN HEMTs has been constrained by stability and reliability issues related to traps. In this article, the locations and energy levels of traps in GaN HEMTs are summarized. Moreover, the characterization techniques for bulk traps and interface traps, whose characteristics and scopes are included as well, are reviewed and highlighted. Finally, the challenges in trap characterization techniques for GaN-based HEMTs are discussed to provide insights into the reliability assessment of GaN-based HEMTs.

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Section: Drain Current Transientmentioning

confidence: 99%

Trap Characterization Techniques for GaN-Based HEMTs: A Critical Review

Zou,

Yang,

Qiao

et al. 2023

Micromachines

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“…In addition to these, to capture the unintentional C-doping from the growth chamber, acceptor-type bulk traps with E T = E C -0.14 eV and a density of 9 × 10 12 cm −3 [29,48] were also defined. Finally, as demonstrated by Malik et al [49], an acceptor trap density of 1 × 10 12 cm −2 and E T = E C -0.2 eV was also defined at the channel interface to capture the shift in V P with applied electrical stress.…”

Section: Simulation Frameworkmentioning

confidence: 99%

Efficacy of back barrier engineered Π-gate InAlN/GaN high electron mobility transistors for high-power applications

Sehra

Anand

Saraswat

et al. 2023

J. Phys. D: Appl. Phys.

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This work investigates the thin barrier InAlN/GaN HEMTs for high power applications through TCAD simulations. To begin with, the TCAD simulations were first calibrated with the in – house fabricated InAlN HEMT sample for both DC and Pulsed characteristics. The thin barrier InAlN/GaN HEMTs shows a large leakage current through the gate electrode due to a high gate injection which severely degrades the breakdown characteristics of the device and thus acts as a bottleneck for high power applications. To improve the 2DEG confinement and to consequently reduce the bulk leakage, back – barrier technique is used. The resistive GaN buffer is replaced with AlGaN back – barrier which improves the breakdown characteristics at the cost of output power density. Thus, to scale up the output power density, and further optimize the breakdown characteristics, a Π – shaped Gate is introduced to limit the gate leakage current through the InAlN barrier by virtue of its improved hot electron reliability. Coupled with the AlGaN back – barrier, the Π – Gate significantly improves the breakdown characteristics for achieving high output power densities, albeit with minor trade – offs to the device gain. To elucidate the compatibility towards high power applications, all the device architectures are dynamically characterized by Pulsed IV simulations and the trap related dispersive effects are investigated. Amongst all, the Π – shaped Gate coupled with the AlGaN back – barrier outperforms the conventional architectures by exercising superior electrostatic control over the channel and exhibiting a high linearity for high power mm – Wave applications.

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