Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)

Abstract

Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Successes and frontiers in extreme UV patterning

“…In this way we can achieve much tighter yield distributions because of tighter variances at reduced complexity. 5,6 In an example of this approach (see Figure 2) we took a cutout layer of a fin field-effect transistor device (which would normally require four 193i-based processes) and replaced it with one EUV-based process, at 7nmmode dimensions.…”

EUV patterning successes and frontiers

“…Though development of photoresists for EUV has been taking place for over a decade [1,2], much less has been explored regarding integration of EUV lithography into the whole patterning process [3], to the point of actually yielding semiconductor devices at a feature scaling that is advantageous over 193 immersion multi-patterning schemes. Indeed, now in the last 1-2 years, there has been major advancement in the integration and yield demonstration of EUV patterning as a replacement for >40nm pitch litho-etch-litho-etch BEOL metal patterning [4], as well as <40nm pitch BEOL metal patterning [5]. These initial demonstrations have shown the promise of EUV-based patterning, as well as the relatively fast development cycle to get there.…”