TriMedia CPU64 application domain and benchmark suite

Riemens, A. K.; Vissers, Kees; Schutten, R.J.; Sijstermans, Frans; Hekstra, G.J.; Hei, G.D. La

doi:10.1109/iccd.1999.808600

Cited by 6 publications

(2 citation statements)

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“…Our benchmark suite consisted of multimedia C programs optimized for the TriMedia VLIW media processor, which features a rich SIMD operation set [14] [15]. To cover a significant area of the application domain, the benchmarks were chosen from different media application categories, see Table 1.…”

Section: Benchmarksmentioning

confidence: 99%

Cluster assignment of global values for clustered VLIW processors

Terechko

Thénaff

Corporaal

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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In this paper high-level language (HLL) variables that are alive in a whole HLL function, across multiple scheduling units, are termed as global values. Due to their long live ranges and, hence, large impact on the schedule, the global values require different compiler optimizations than local values, which span across only one scheduling unit. The instruction scheduler for a clustered ILP processor, which is responsible for cluster assignment of operations and variables, faces a difficult problem of assigning global values to clusters. Our study shows that trivial assignments (e.g. mapping all global values into one cluster) may result in a severe cycle count overhead relative to the unicluster of up to 26.3% for a four cluster VLIW machine. This paper presents three advanced algorithms for assigning global values to clusters based on multi-pass scheduling and affinity of variables. Furthermore, we measure performance of these algorithms on optimized multimedia C applications and assess quality of our algorithms by comparing them to a practical higher performance bound derived from a vast random search. Our algorithms reduce the execution time overhead of the best simple algorithm round-robin from 10.5% to 5.9% for the two cluster VLIW machine and from 17.3% to 14.12% for the four cluster VLIW machine.

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Section: Benchmarksmentioning

confidence: 99%

Cluster assignment of global values for clustered VLIW processors

Terechko

Thénaff

Corporaal

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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“…This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Given the fact that the experimental TriMedia is a 5 issue-slot VLIW processor with 64-bit datapaths and a very rich multimedia-oriented instruction set [1], such an improvement within its target media processing domain [3] indicates that augmenting TriMedia with an FPGA shows clear benefit for doing 2-D IDCT.…”

Section: Introductionmentioning

confidence: 98%

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

Sima

Cotöfană

Eijndhoven

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Keywords: configurable computing, VLIW processor, field-programmable gate array, inverse discrete cosine transform 196 Sima et al.

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